Patents by Inventor Toshiki Hikosaka
Toshiki Hikosaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180329236Abstract: According to one embodiment, a waveguide element includes a first crystal region, and a second crystal region. The first crystal region extends in a first direction and includes a first nitride semiconductor. The second crystal region extends in the first direction, includes a second nitride semiconductor, and is continuous with the first crystal region. A second direction crosses the first direction. The second direction is from the first crystal region toward the second crystal region. A <0001> direction of the first crystal region is from the first crystal region toward the second crystal region. A <0001> direction of the second crystal region is from the second crystal region toward the first crystal region.Type: ApplicationFiled: February 22, 2018Publication date: November 15, 2018Applicant: Kabushiki Kaisha ToshibaInventor: Toshiki HIKOSAKA
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Publication number: 20180308940Abstract: According to one embodiment, a semiconductor wafer includes a substrate, an AlN buffer layer, a foundation layer, a first high Ga composition layer, a high Al composition layer, a low Al composition layer, an intermediate unit and a second high Ga composition layer. The first layer is provided on the foundation layer. The high Al composition layer is provided on the first layer. The low Al composition layer is provided on the high Al composition layer. The intermediate unit is provided on the low Al composition layer. The second layer is provided on the intermediate unit. The first layer has a first tensile strain and the second layer has a second tensile strain larger than the first tensile strain. Alternatively, the first layer has a first compressive strain and the second layer has a second compressive strain smaller than the first compressive strain.Type: ApplicationFiled: May 18, 2018Publication date: October 25, 2018Applicant: ALPAD CORPORATIONInventors: Yoshiyuki Harada, Toshiki Hikosaka, Hisashi Yoshida, Hung Hung, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 10008571Abstract: According to one embodiment, a semiconductor wafer includes a substrate, an AlN buffer layer, a foundation layer, a first high Ga composition layer, a high Al composition layer, a low Al composition layer, an intermediate unit and a second high Ga composition layer. The first layer is provided on the foundation layer. The high Al composition layer is provided on the first layer. The low Al composition layer is provided on the high Al composition layer. The intermediate unit is provided on the low Al composition layer. The second layer is provided on the intermediate unit. The first layer has a first tensile strain and the second layer has a second tensile strain larger than the first tensile strain. Alternatively, the first layer has a first compressive strain and the second layer has a second compressive strain smaller than the first compressive strain.Type: GrantFiled: October 23, 2015Date of Patent: June 26, 2018Assignee: ALPAD CORPORATIONInventors: Yoshiyuki Harada, Toshiki Hikosaka, Hisashi Yoshida, Hung Hung, Naoharu Sugiyama, Shinya Nunoue
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Publication number: 20180174849Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, and first, second, third, fourth, and fifth semiconductor regions. The first electrode includes a first conductive region. The second electrode includes a second conductive region separated. The third electrode includes a third conductive region. The first semiconductor region is separated from the first, second, and third conductive regions. The second semiconductor region is provided between the first conductive and semiconductor regions, between the second conductive and first semiconductor regions, and between the third conductive and first semiconductor regions. The third semiconductor region is provided between the first conductive region and the second semiconductor region. The fourth semiconductor region is provided between the second conductive region and the second semiconductor region.Type: ApplicationFiled: August 7, 2017Publication date: June 21, 2018Applicant: Kabushiki Kaisha ToshibaInventors: Kenjiro UESUGI, Toshiki HIKOSAKA, Shinya NUNOUE
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Patent number: 9679974Abstract: According to one embodiment, a nitride semiconductor element includes: a stacked body; and a functional layer. The stacked body includes a first GaN layer, a first layer, and a second GaN layer. The first GaN layer includes a first protrusion. The first layer is provided on the first GaN layer and contains at least one of Si and Mg. The second GaN layer is provided on the first layer and includes a second protrusion. Length of bottom of the second protrusion is shorter than length of bottom of the first protrusion. A functional layer is provided on the stacked body and includes a nitride semiconductor.Type: GrantFiled: June 24, 2014Date of Patent: June 13, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Hikosaka, Hisashi Yoshida, Hajime Nago, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 9673284Abstract: According to one embodiment, a nitride semiconductor device includes a stacked body and a functional layer. The stacked body includes an AlGaN layer of AlxGa1-xN (0<x?1), a first Si-containing layer, a first GaN layer, a second Si-containing layer, and a second GaN layer. The first Si-containing layer contacts an upper surface of the AlGaN layer. The first Si-containing layer contains Si at a concentration not less than 7×1019/cm3 and not more than 4×1020/cm3. The first GaN layer is provided on the first Si-containing layer. The first GaN layer includes a protrusion having an oblique surface tilted with respect to the upper surface. The second Si-containing layer is provided on the first GaN layer. The second Si-containing layer contains Si. The second GaN layer is provided on the second Si-containing layer. The functional layer is provided on the stacked body. The functional layer includes a nitride semiconductor.Type: GrantFiled: April 16, 2015Date of Patent: June 6, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Hikosaka, Yoshiyuki Harada, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 9601662Abstract: According to an embodiment, a semiconductor light emitting device includes a foundation layer, a first semiconductor layer, a light emitting layer, and a second semiconductor layer. The foundation layer has an unevenness having recesses, side portions, and protrusions. A first major surface of the foundation layer has an overlay-region. The foundation layer has a plurality of dislocations including first dislocations whose one ends reaching the recess and second dislocations whose one ends reaching the protrusion. A proportion of a number of the second dislocations reaching the first major surface to a number of all of the second dislocations is smaller than a proportion of a number of the first dislocations reaching the first major surface to a number of all of the first dislocations. A number of the dislocations reaching the overlay-region of the first major surface is smaller than a number of all of the first dislocations.Type: GrantFiled: October 15, 2015Date of Patent: March 21, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Toshiki Hikosaka, Yoshiyuki Harada, Maki Sugai, Shinya Nunoue
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Patent number: 9590141Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, a light emitting part, and a p-side electrode. The light emitting part is provided between the n-type and the p-type semiconductor layers, and includes a plurality of barrier layers and a plurality of well layers. The p-side electrode contacts the p-type semiconductor layer. The p-type semiconductor layer includes first, second, third, and fourth p-type layers. The first p-type layer contacts the p-side electrode. The second p-type layer contacts the light emitting part. The third p-type layer is provided between the first p-type layer and the second p-type layer. The fourth p-type layer is provided between the second p-type layer and the third p-type layer. The second p-type layer contains Al and contains a p-type impurity in a lower concentration lower than that in the first concentration.Type: GrantFiled: June 8, 2015Date of Patent: March 7, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Tachibana, Hajime Nago, Toshiki Hikosaka, Shigeya Kimura, Shinya Nunoue
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Publication number: 20170025578Abstract: According to one embodiment, a nitride semiconductor element includes a p-type semiconductor layer and a p-side electrode. The p-type semiconductor layer includes a nitride semiconductor, and has a first surface. The p-side electrode contacts the first surface. The first surface is a semi-polar plane. The first surface includes a plurality of protrusions. A height of the protrusions along a first direction is not less than 1 nanometer and not more than 5 nanometers. The first direction is from the p-type semiconductor layer toward the p-side electrode. A density of the protrusions in the first surface is more than 1.0×1010/cm2 and not more than 6.1×1010/cm2.Type: ApplicationFiled: February 25, 2016Publication date: January 26, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Toshiki HIKOSAKA, Hisashi Yoshida, Kenjiro Uesugi, Hiroshi Ono, Shinya Nunoue
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Patent number: 9515146Abstract: According to one embodiment, a nitride semiconductor layer spreading along a first surface is provided. The nitride semiconductor layer includes a first region and a second region. A length of the first region in a first direction parallel to the first surface is longer than a length of the first region in a second direction parallel to the first surface and perpendicular to the first direction. The second region is arranged with the first region in the second direction. A length of the second region in the first direction is longer than a length of the second region in the second direction. A c-axis being is tilted with respect to the second direction for the first region and the second region. The c-axis intersects a third direction perpendicular to the first surface.Type: GrantFiled: May 1, 2015Date of Patent: December 6, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Hikosaka, Hiroshi Ono, Shinya Nunoue
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Patent number: 9508804Abstract: According to one embodiment, a nitride semiconductor element includes a foundation layer, a functional layer and a stacked body. The stacked body is provided between the foundation layer and the functional layer. The stacked body includes a first stacked intermediate layer including a first GaN intermediate layer, a first high Al composition layer of Alx1Ga1-x1N (0<x1?1) and a first low Al composition layer. A compressive strain is applied to the first low Al composition layer. Unstrained GaN has a first lattice spacing. The Alx1Ga1-x1N (0<x1?1) when unstrained has a second lattice spacing. The first high Al composition layer has a third lattice spacing. An Al composition ratio of the first low Al composition layer is not more than a ratio of a difference between the first and third lattice spacings to a difference between the first and second lattice spacings.Type: GrantFiled: February 16, 2016Date of Patent: November 29, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Toshiki Hikosaka, Yoshiyuki Harada, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 9397167Abstract: A nitride semiconductor wafer includes a silicon substrate, a stacked multilayer unit, a silicon-containing unit, and an upper layer unit. The silicon substrate has a major surface. The stacked multilayer unit is provided on the major surface. The stacked multilayer unit includes N number of buffer layers. The buffer layers include an i-th buffer layer, and an (i+1)-th buffer layer provided on the i-th buffer layer. The i-th buffer layer has an i-th lattice length Wi in a first direction parallel to the major surface. The (i+1)-th buffer layer has an (i+1)-th lattice length W(i+1) in the first direction. A relation that (W(i+1)?Wi)/Wi?0.008 is satisfied for all the buffer layers. The silicon-containing unit is provided on the stacked multilayer unit. The upper layer unit is provided on the silicon-containing unit.Type: GrantFiled: December 28, 2012Date of Patent: July 19, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hisashi Yoshida, Toshiki Hikosaka, Yoshiyuki Harada, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 9391145Abstract: According to one embodiment, a nitride semiconductor element includes a functional layer and a stacked body. The stacked body includes a GaN intermediate layer, a low Al composition layer, a high Al composition layer, and a first Si-containing layer. The low Al composition layer includes a nitride semiconductor having a first Al composition ratio. The low Al composition layer is provided between the GaN intermediate layer and the functional layer. The high Al composition layer includes a nitride semiconductor having a second Al composition ratio. The high Al composition layer is provided between the GaN intermediate layer and the low Al composition layer. The second Al composition ratio is higher than the first Al composition ratio. The first Si-containing layer is provided between the GaN intermediate layer and the high Al composition layer.Type: GrantFiled: January 9, 2015Date of Patent: July 12, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Hikosaka, Hisashi Yoshida, Hajime Nago, Shinya Nunoue
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Publication number: 20160163803Abstract: According to one embodiment, a nitride semiconductor element includes a foundation layer, a functional layer and a stacked body. The stacked body is provided between the foundation layer and the functional layer. The stacked body includes a first stacked intermediate layer including a first GaN intermediate layer, a first high Al composition layer of Alx1Ga1-x1N (0<x1?1) and a first low Al composition layer. A compressive strain is applied to the first low Al composition layer. Unstrained GaN has a first lattice spacing. The Alx1Ga1-x1N (0<x1?1) when unstrained has a second lattice spacing. The first high Al composition layer has a third lattice spacing. An Al composition ratio of the first low Al composition layer is not more than a ratio of a difference between the first and third lattice spacings to a difference between the first and second lattice spacings.Type: ApplicationFiled: February 16, 2016Publication date: June 9, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Toshiki HIKOSAKA, Yoshiyuki HARADA, Hisashi YOSHIDA, Naoharu SUGIYAMA, Shinya NUNOUE
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Patent number: 9349590Abstract: According to one embodiment, a method for manufacturing a nitride semiconductor layer is disclosed. The method can include forming a first lower layer on a major surface of a substrate and forming a first upper layer on the first lower layer. The first lower layer has a first lattice spacing along a first axis parallel to the major surface. The first upper layer has a second lattice spacing along the first axis larger than the first lattice spacing. At least a part of the first upper layer has compressive strain. A ratio of a difference between the first and second lattice spacing to the first lattice spacing is not less than 0.005 and not more than 0.019. A growth rate of the first upper layer in a direction parallel to the major surface is larger than that in a direction perpendicular to the major surface.Type: GrantFiled: September 5, 2012Date of Patent: May 24, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Hikosaka, Yoshiyuki Harada, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 9324916Abstract: According to one embodiment, a semiconductor light emitting device includes an electrode layer, a first semiconductor layer, a first elongated electrode, a second semiconductor layer, and a light emitting layer. The first semiconductor layer includes a crystal having a cleavage plane. The first semiconductor layer includes a first thin film portion and a thick film portion. The first thin film portion extends in a first direction perpendicular to a stacking direction from the electrode layer toward the first semiconductor layer. The first thin film portion has a first thickness. The thick film portion is arranged with the first thin film portion in a plane perpendicular to the stacking direction. An angle between the first direction and the cleavage plane is not less than 3 degrees and not more than 27 degrees. The first elongated electrode extends in the first direction in contact with the first thin film portion.Type: GrantFiled: September 29, 2015Date of Patent: April 26, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Jumpei Tajima, Kotaro Zaima, Toshiki Hikosaka, Hiroshi Ono, Naoharu Sugiyama, Shinya Nunoue
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Patent number: 9305773Abstract: According to one embodiment, a semiconductor device includes a functional layer of a nitride semiconductor. The functional layer is provided on a nitride semiconductor layer including a first stacked multilayer structure provided on a substrate. The first stacked multilayer structure includes a first lower layer, a first intermediate layer, and a first upper layer. The first lower layer contains Si with a first concentration and has a first thickness. The first intermediate layer is provided on the first lower layer to be in contact with the first lower layer, contains Si with a second concentration lower than the first concentration, and has a second thickness thicker than the first thickness. The first upper layer is provided on the first intermediate layer to be in contact with the first intermediate layer, contains Si with a third concentration lower than the second concentration, and has a third thickness.Type: GrantFiled: June 19, 2015Date of Patent: April 5, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hung Hung, Naoharu Sugiyama, Hisashi Yoshida, Toshiki Hikosaka, Yoshiyuki Harada, Shinya Nunoue
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Patent number: 9287369Abstract: According to one embodiment, a nitride semiconductor element includes a foundation layer, a functional layer and a stacked body. The stacked body is provided between the foundation layer and the functional layer. The stacked body includes a first stacked intermediate layer including a first GaN intermediate layer, a first high Al composition layer of Alx1Ga1-x1N (0<x1?1) and a first low Al composition layer. A compressive strain is applied to the first low Al composition layer. Unstrained GaN has a first lattice spacing. The Alx1Ga1-x1N (0<x1?1) when unstrained has a second lattice spacing. The first high Al composition layer has a third lattice spacing. An Al composition ratio of the first low Al composition layer is not more than a ratio of a difference between the first and third lattice spacings to a difference between the first and second lattice spacings.Type: GrantFiled: January 14, 2014Date of Patent: March 15, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Toshiki Hikosaka, Yoshiyuki Harada, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue
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Publication number: 20160056329Abstract: According to one embodiment, a semiconductor light emitting element includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type separated from the first semiconductor layer in a first direction, a light emitting layer provided between the first and second semiconductor layers, and a first intermediate unit provided between the first semiconductor layer and the light emitting layer. The light emitting layer includes a well layer including a nitride semiconductor including In. The first intermediate unit includes stacked bodies. The stacked bodies are arranged in the first direction. Each of the stacked bodies includes a first layer of Inx1Ga1-x1N, a second layer of Aly1Ga1-y1N provided between the first layer and the light emitting layer to contact the first layer, and a third layer of Aly2Ga1-y2N provided between the second layer and the light emitting layer to contact the second layer.Type: ApplicationFiled: May 18, 2015Publication date: February 25, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Hisashi YOSHIDA, Toshiki Hikosaka, Shigeya Kimura, Hajime Nago, Shinya Nunoue
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Patent number: 9263631Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type layer, a p-type layer, and a light emitting unit provided between the n-type layer and the p-type layer and including barrier layers and well layers. At least one of the barrier layers includes first and second portion layers. The first portion layer is disposed on a side of the n-type layer. The second portion layer is disposed on a side of the p-type layer, and contains n-type impurity with a concentration higher than that in the first portion layer. At least one of the well layers includes third and fourth portion layers. The third portion layer is disposed on a side of the n-type layer. The fourth portion layer is disposed on a side of the p-type layer, and contains n-type impurity with a concentration higher than that in the third portion layer.Type: GrantFiled: July 30, 2014Date of Patent: February 16, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Toshiki Hikosaka, Koichi Tachibana, Hajime Nago, Shinya Nunoue