Patents by Inventor Toshiki Naito

Toshiki Naito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050067293
    Abstract: A producing method of a flexible wired circuit board that can prevent the formation of a gap between an elongate substrate and a stiffener sheet bonded thereto to prevent contamination of the flexible wired circuit board obtained. In the process subsequent to the process of forming a conductive pattern 3 on a surface of the elongate substrate 1 by the semi-additive process using electrolysis plating and then annealing the elongate substrate 1 with the conductive pattern 3 in its wound up state, a stiffener sheet 9 having a width narrower than the elongate substrate 1 is bonded to the back side of the elongate substrate 1. Thereafter, an oxidized film formed on a surface of the conductive pattern 3 is removed and then a solder resist 11 is formed thereon. This prevents the strip of the stiffener sheet 9 from the elongate substrate 1 and in turn prevents etching solution or developing solution from entraining in a gap therebetween.
    Type: Application
    Filed: September 28, 2004
    Publication date: March 31, 2005
    Inventors: Toshiki Naito, Yoshifumi Shinogi, Takeshi Yamato
  • Publication number: 20050062160
    Abstract: The invention provides a double-sided wiring circuit board which comprises: an insulating layer having a through-hole formed therein and having a first side and a second side; a conductor layer formed on the first side of the insulating layer; a thin metal film formed on the second side of the insulating layer, on the inner circumferential surface of the through-hole, and on the part of the conductor layer that is located in the through-hole; and a deposit layer formed by electroplating on the thin metal film, wherein the through-hole has an inner circumferential wall which inclines so that the inner diameter of the hole gradually increases from the first side to the second side of the insulating layer, and wherein the angle of the inclination between the first side of the insulating layer and the inner circumferential wall being from 40° to 70°. Also disclosed is a production process thereof.
    Type: Application
    Filed: August 18, 2004
    Publication date: March 24, 2005
    Inventors: Toshiki Naito, Toshihiko Omote
  • Publication number: 20050053868
    Abstract: The invention provides a process for producing a wiring circuit board, which comprises the steps of: (A) forming a conductor layer of a predetermined pattern on an insulating layer; (B) forming a photosensitive solder resist layer on the insulating layer and the patterned conductor layer formed on the insulating layer; (C) disposing a transparent protective film on the photosensitive solder resist layer; and (D) exposing the photosensitive solder resist layer to a light through the transparent protective film.
    Type: Application
    Filed: September 7, 2004
    Publication date: March 10, 2005
    Inventor: Toshiki Naito
  • Publication number: 20040224436
    Abstract: A method of producing TAB tape carrier that can produce TAB tape carrier in such a way as to prevent undulation at a split end surface thereof and tear of circuit pattern thereat, thereby producing the TAB tape carrier of high reliability with increased efficiency. In the method, an insulating layer 2 is formed on an elongate metal supporting layer 1 by application of resin solution to the metal supporting layer 1 and by drying, first. Then, a plurality of lines of wiring patterns 3 are formed on the insulating layer 2 in a semi-additive process. Thereafter, slit grooves S are formed in the metal supporting layer 1 in spaces between adjacent lines of wiring patterns 3. Then, the insulating layer 2 is split along the slit grooves S to divide the continuous sheet into individual strips, thereby producing the TAB tape carriers 12.
    Type: Application
    Filed: May 6, 2004
    Publication date: November 11, 2004
    Inventor: Toshiki Naito
  • Publication number: 20040221448
    Abstract: A method for producing a wired circuit board that can provide improved productivity and economical efficiency, while preventing the forming failure of the wired circuit board due to which when a conductor layer is formed by plating, the plating material is caused to penetrate under the plating resist or the plating resist is caused to strip. In the method, after a thin conductor film 2 is formed on an insulating base layer 1, liquid solution of photosensitive resist is applied to the thin conductor film 2 and then dried, thereby forming the first plating resist layer 3 on the thin conductor film 2. Then, a film of photosensitive resist is adhesively bonded to the first plating resist layer 3, thereby forming the second plating resist layer 4. Thereafter, the first and the second plating resist layers 3, 4 are formed into a reversal pattern to a wired circuit pattern by a photographic process.
    Type: Application
    Filed: April 29, 2004
    Publication date: November 11, 2004
    Inventors: Toshiki Naito, Hiroshi Yamazaki, Takeshi Yamato
  • Publication number: 20040207069
    Abstract: Only individual piece-like flexible wiring boards 1 produced separately and judged to be non-defective products in an inspection step in advance are mounted at regular intervals on a carrying support film 7 to thereby obtain a TAB tape carrier. According to this method, the yield on continuous production can be improved while the step of replacing defective flexible wiring boards found by inspection with non-defective flexible wiring boards can be omitted after mounting of the flexible wiring boards 1. A difference in level between the respective flexible wiring boards can be prevented from being caused by the replacement, so that high connection reliability can be ensured.
    Type: Application
    Filed: December 8, 2003
    Publication date: October 21, 2004
    Applicant: NITTO DENKO CORPORATION
    Inventors: Toshiki Naito, Toshihiko Omote, Hiroshi Yamazaki
  • Publication number: 20030221314
    Abstract: A method for manufacturing a double-sided circuit board from a board material having a first electric conductor layer and a first electrically insulating layer, including the steps of: making conduction holes in the board material so as to penetrate only the first electrically insulating layer or both the first electrically insulating layer and the first electric conductor layer; forming an electrically conductive thin-film layer on a surface of the first electrically insulating layer and wall surfaces of the conduction holes; forming a second electrically insulating layer on the electrically conductive thin-film layer; forming a first electric conductor wiring by electroplating on predetermined portions of the electrically conductive thin-film layer; covering the first electric conductor wiring with a chemical-resistant film; forming a second electric conductor wiring by chemically dissolving a predetermined portion of another surface of the first electric conductor layer; and removing the second electricall
    Type: Application
    Filed: February 5, 2003
    Publication date: December 4, 2003
    Applicant: NITTO DENKO CORPORATION
    Inventors: Toshiki Naito, Yoshifumi Shinogi, Daisuke Uenda
  • Patent number: 6157084
    Abstract: A semiconductor device capable of meeting the demand for fine-pitched wiring of semiconductor element and highly dense mounting thereof, as well as the demand for a thin structure thereof, which device being superior in the adhesion property of an insulating resin to be used for sealing a semiconductor element and a film carrier, and thus highly reliable. In FIG. 1, a conductive circuit (5) is embedded so that it will not be exposed at the both surfaces (6a, 6b) of an insulator layer (6), and conductive paths (7, 8) are formed in a pair from the both surfaces (5a, 5b) of the conductive circuit (5), the conductive paths slipping relative to each other in the direction of the surface of the conductive circuit (5). The conductive paths (7, 8) are respectively connected to bumps (9, 10), and the conductive circuit (5) and bumps (9, 10) are conducted via conductive paths (7, 8).
    Type: Grant
    Filed: September 17, 1997
    Date of Patent: December 5, 2000
    Assignee: Nitto Denko Corporation
    Inventors: Atsushi Hino, Toshiki Naito, Masakazu Sugimoto
  • Patent number: 6017438
    Abstract: A method for producing a circuit substrate having a bump contact point, comprising the steps of (a) disposing a positive electrode in a plating solution stored in a storage tank, (b) exposing a conductive circuit formed on an insulating substrate, above the surface of the plating solution, (c) disposing a jet stream opening below the surface of the plating solution, and (d) spouting out the plating solution from the jet stream opening toward the negative electrode for electroplating using said conductive circuit as a negative electrode, to form the bump contact point on the surface of the negative electrode, and a jet stream type plating apparatus used therefor. According to the present invention, mixing of air bubbles in the plating solution can be inhibited, which in turn enables suppression of oxidative decomposition of the brightener components. As a consequence, the bump contact point can have a mushroom shape, and variation in the height of the bump contact points can be minimized.
    Type: Grant
    Filed: September 26, 1997
    Date of Patent: January 25, 2000
    Assignee: Nitto Denko Corporation
    Inventors: Yoshinari Takayama, Toshiki Naito, Kazuo Ouchi
  • Patent number: 6011310
    Abstract: Disclosed are a film carrier comprising an insulating layer having laid therein an electrically conductive circuit such that the circuit is not exposed on the surface thereof, wherein conductive passages from the conductive circuit to one surface of the insulating layer are formed in the insulating layer and via holes from said conductive circuit to the other surface of the insulating layer are formed and a semiconductor device prepared by mounting a semiconductor element on the insulating layer of the film carrier. The film carrier can sufficiently correspond to pitch-fining and high-density mounting of a semiconductor element wiring, can surely perform the connecting operation of inner lead bonding and outer lead bonding and gives the mounting area of as small as possible.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: January 4, 2000
    Assignee: Nitto Denko Corporation
    Inventors: Toshiki Naito, Kazuo Ouchi
  • Patent number: 5374469
    Abstract: A flexible printed substrate imparted with an adhesive property for loading on an external substrate, a double printed substrate having formed on both surfaces thereof a metal layer or a wiring circuit, and a multilayer substrate having a multilayer structure are disclosed. The flexible printed substrate comprises an insulating resin layer comprising a low-linear expansion polyimide resin layer and a thermoplastic polyimide resin layer, and a metal layer or a wiring circuit formed on the low-linear expansion polyimide resin layer of the insulating resin layer, wherein a mixed region of the polyimide resin components is formed in the interface between the low-linear expansion polyimide resin layer and the thermoplastic polyimide resin layer.
    Type: Grant
    Filed: September 17, 1992
    Date of Patent: December 20, 1994
    Assignee: Nitto Denko Corporation
    Inventors: Atsushi Hino, Amane Mochizuki, Kazuo Ouchi, Shoji Morita, Toshiki Naito, Kazumi Higashi, Masako Maeda, Masayuki Kaneto, Munekazu Tanaka, Masakazu Sugimoto