Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells each including a resistance change type memory element configured to store a resistance state and a switch, a read determination circuit that compares a measurement signal from the memory cell selected in the memory cell array with a reference signal to determine a resistance state so as to read information from the resistance change type memory element, and a reference signal correction unit that corrects a level of the reference signal based on a selected position of the memory cell in the memory cell array.

Abstract: According to one embodiment, a switching power circuit compares a reference voltage with a feedback voltage of an output voltage, and controls the output voltage in accordance with the reference voltage, in which in a case where the output current is greater than a predetermined set current, the voltage of the reference voltage is decreased.

Abstract: A rectangular-wave-signal generating circuit according to an embodiment comprises: a sawtooth-wave output circuit; a first detector; a second detector; and a first PWM-signal output circuit. The sawtooth-wave output circuit is configured to generate and output a sawtooth-wave signal synchronized with a clock signal. The first detector is configured to detect a first timing at which a potential of the sawtooth-wave signal exceeds a bottom potential. The second detector is configured to detect a second timing at which a potential of the sawtooth-wave signal exceeds a potential of a first pulse-width instruction voltage signal. The first PWM-signal output circuit is configured to generate a first PWM signal based on a time difference between the first timing and the second timing.

Abstract: According to one embodiment, a switching power circuit compares a reference voltage with a feedback voltage of an output voltage, and controls the output voltage in accordance with the reference voltage, in which in a case where the output current is greater than a predetermined set current, the voltage of the reference voltage is decreased.

Abstract: According to one embodiment, a switching power circuit, includes: a switching transistor that is connected between an input terminal and a node; a driving circuit that supplies a PWM driving signal to the switching transistor; and a phase compensation circuit that supplies a feedback voltage to an error amplifier, in which the properties of the phase compensation circuit are switched in accordance with the voltage of the node immediately before the switching transistor is turned on.

Abstract: A rectangular-wave-signal generating circuit according to an embodiment comprises: a sawtooth-wave output circuit; a first detector; a second detector; and a first PWM-signal output circuit. The sawtooth-wave output circuit is configured to generate and output a sawtooth-wave signal synchronized with a clock signal. The first detector is configured to detect a first timing at which a potential of the sawtooth-wave signal exceeds a bottom potential. The second detector is configured to detect a second timing at which a potential of the sawtooth-wave signal exceeds a potential of a first pulse-width instruction voltage signal. The first PWM-signal output circuit is configured to generate a first PWM signal based on a time difference between the first timing and the second timing.

Abstract: According to one embodiment, a switching power circuit, includes: a switching transistor that is connected between an input terminal and a node; a driving circuit that supplies a PWM driving signal to the switching transistor; and a phase compensation circuit that supplies a feedback voltage to an error amplifier, in which the properties of the phase compensation circuit are switched in accordance with the voltage of the node immediately before the switching transistor is turned on.

Abstract: According to one embodiment, a switching power circuit compares a reference voltage with a feedback voltage of an output voltage, and controls the output voltage in accordance with the reference voltage, in which in a case where the output current is greater than a predetermined set current, the voltage of the reference voltage is decreased.

Abstract: According to an embodiment, a constant voltage power source circuit has a voltage feedback circuit that controls an output voltage depending on a control voltage. It has a current feedback circuit that detects an output current, keeps the control voltage at a constant voltage until the output current reaches a predetermined current value, and changes a value of the control voltage at a time when the output current reaches the predetermined current value.

Abstract: A switched-mode power supply according to an embodiment comprises a switching circuit, a smoothing circuit, a differential-signal output circuit, a signal output circuit, a pulse-drive signal output circuit, and a signal generation circuit. The differential-signal output circuit is configured to output a differential signal based on a potential difference between the output voltage and a reference potential. The signal output circuit is configured to generate a signal synchronous. The pulse-drive signal output circuit is configured to adjust a time ratio of outputting the voltage on a basis of a time point when the differential signal and the signal have a same value. The signal generation circuit is configured to generate at least either the differential signal or the signal to cause an interval from a base time in one cycle of the clock signal to the time point to decrease as the input voltage increases.

Abstract: According to an embodiment, a constant voltage power source circuit has a voltage feedback circuit that controls an output voltage depending on a control voltage. It has a current feedback circuit that detects an output current, keeps the control voltage at a constant voltage until the output current reaches a predetermined current value, and changes a value of the control voltage at a time when the output current reaches the predetermined current value.

Abstract: A DC-DC converter includes a first switch connected between an input node and a switching node, a second switch connected between a reference node and the switching node, a capacitor having a first terminal connected to one of the input node and the reference node, a transformer including a primary coil connected between the switching node and a second terminal of the capacitor, and a secondary coil, a rectification smoothing circuit that rectifies and smooths a voltage of the secondary coil, and a drive circuit. The drive circuit alternately turns on the first and second switches, such that a dead time during which both the first and second switches are turned off has a length corresponding to a time period during which a voltage of the switching node is transitioning from a low state to a high state or the high state to the low state.

Abstract: A DC-DC converter includes a first switch connected between an input node and a switching node, a second switch connected between a reference node and the switching node, a capacitor having a first terminal connected to one of the input node and the reference node, a transformer including a primary coil connected between the switching node and a second terminal of the capacitor, and a secondary coil, a rectification smoothing circuit that rectifies and smooths a voltage of the secondary coil, and a drive circuit. The drive circuit alternately turns on the first and second switches, such that a dead time during which both the first and second switches are turned off has a length corresponding to a time period during which a voltage of the switching node is transitioning from a low state to a high state or the high state to the low state.

Abstract: A first added signal that is acquired by adding a reference current signal that is in proportion to a current flowing through an inductance element, a slope compensation signal and a voltage difference signal that is in proportion to a difference between an input voltage and an output voltage and a second added signal that is acquired by adding the reference current signal and the slope compensation signal are compared with a difference signal of a voltage that is in proportion to the output voltage and a predetermined reference voltage, and pulse widths of driving pulse signals of a step-down switching circuit and a step-up switching circuit are controlled as a result of the comparison.

Abstract: A DC-DC converter has a switching element, a lowpass filter, an oscillator, an AD converter, an error signal generator, a counter, a comparator, a selector configured to select one of the plurality of clock signals in accordance with a value of a lower side bit of the error signal in sync with a timing when the comparator detects coincidence, and a switching controller configured to control ON/OFF of the switching element in accordance with the clock signal selected by the selector. The selector selects one among the plurality of clock signals and a new clock signal generated by combining two or more clock signals comprising neighboring phases among the plurality of clock signals.

Abstract: A first added signal that is acquired by adding a reference current signal that is in proportion to a current flowing through an inductance element, a slope compensation signal and a voltage difference signal that is in proportion to a difference between an input voltage and an output voltage and a second added signal that is acquired by adding the reference current signal and the slope compensation signal are compared with a difference signal of a voltage that is in proportion to the output voltage and a predetermined reference voltage, and pulse widths of driving pulse signals of a step-down switching circuit and a step-up switching circuit are controlled as a result of the comparison.

Abstract: A semiconductor device includes a first terminal, a second terminal, and a fuse link that connects between the first terminal and the second terminal. The first terminal and the fuse link have a polysilicon layer doped with an impurity ion and a layer containing a metal element laminated on the polysilicon layer. The second terminal has a polysilicon layer not doped with an impurity ion and a layer containing a metal element laminated on the polysilicon layer, in at least a part of an end side connected to the fuse link.

Abstract: A DC-DC converter has a switching element, a lowpass filter, an oscillator, an AD converter, an error signal generator, a counter, a comparator, a selector configured to select one of the plurality of clock signals in accordance with a value of a lower side bit of the error signal in sync with a timing when the comparator detects coincidence, and a switching controller configured to control ON/OFF of the switching element in accordance with the clock signal selected by the selector. The selector selects one among the plurality of clock signals and a new clock signal generated by combining two or more clock signals comprising neighboring phases among the plurality of clock signals.

Abstract: A semiconductor memory device includes n stages of memory cell units, sense amplifier units, and shift registers. N units of the shift registers are connected to one another on the left end sides. The signal processing units and the reversed signal processing units are disposed adjacent to one another in each of the n units of the shift registers. The signal processing units located on the odd-numbered positions counted from the input end side are connected to one another. The reversed signal processing units located on the even-numbered positions counted from the input end side are connected to one another. The signal processing units located on the end opposite to the input end side are connected to the reversed signal processing units located on the end opposite to the input end side. Each of the signal processing units includes the logic circuit unit and the flip-flop while each of the reversed signal processing units includes the reversed logic circuit unit and the reversed flip-flop.

Abstract: A nonvolatile semiconductor memory device comprising: a memory cell array in which two bit lines are provided to each one bit of input data, and memory cells each including an anti-fuse element are arranged at an intersection point between one of the two bit lines and an even address word line, and an intersection point between the other one of the two bit lines and an odd address word line, respectively; a plurality of booster circuits which are arranged in a plurality of memory banks, respectively, and each of which generates a write voltage and a read voltage to be supplied to a corresponding one of the anti-fuse elements of the respective memory banks, each of the memory banks obtained by dividing the memory cell array; a booster circuit controller to issue an instruction to generate the write voltage and the read voltage to the plurality of booster circuits; a word line selector to activate a different word line at the time of writing from one to be activated at the time of reading, with respect to the s