Abstract: A multiplexer circuit is composed of several basic unit circuits, which are each supplied with a data signal and select signal. Each output terminal of several basic unit circuits is connected to a common line. Each basic unit circuit is composed of an unmatch detection circuit detecting an unmatch state of the common line and the data signal, a control circuit controlling drive timing of the common line when receiving a state transition of the select signal, and a tri-state buffer driving the common line according to a state of the data signal when an output of the unmatch detection circuit and an output of the control circuit are both in an active state while holds high impedance state when the state other than above is given.

Abstract: A semiconductor integrated circuit device includes a plurality of sense amplifier line pairs, a plurality of sense amplifier latch circuits respectively connected to the sense amplifier line pairs, and a sense amplifier driver circuit which supplies a sense amplifier activation signal to the sense amplifier latch circuits. The sense amplifier driver circuit is provided for each of the plurality of sense amplifier latch circuits and supplies the sense amplifier activation signal to each of the plurality of sense amplifier latch circuits.

Abstract: A semiconductor substrate has a bulk region and a semiconductor region formed either on a buried insulating film or on a cavity region. The bulk region contains a plurality of memory cells, sense amplifiers and column selection gates, while the semiconductor region contains word line selection circuits and column selection circuits.

Abstract: A semiconductor substrate has a bulk region and a semiconductor region formed either on a buried insulating film or on a cavity region. The bulk region contains a plurality of memory cells, sense amplifiers and column selection gates, while the semiconductor region contains word line selection circuits and column selection circuits.

Abstract: An electronic circuit according to this invention includes a first delay compensation circuit which receives a first power supply voltage and a first signal and outputs a first output signal delayed by a first predetermined time, a second delay compensation circuit which receives a second power supply voltage and the first signal and outputs a second output signal delayed by a second predetermined time, a first logic circuit which receives the first power supply voltage and the second output signal output from the second delay compensation circuit and outputs a first operation result by performing first logic operation, and a second logic circuit which receives the second power supply voltage and the first output signal output from the first delay compensation circuit and outputs a second operation result by performing second logic operation.

Abstract: A plurality of wirings are arranged approximately in parallel. A first amplifier is arranged in one wiring of the two adjacent wirings which are included in the plurality of wirings. The first amplifier is arranged at least at a position which divides the interval of a predetermined distance of one wiring by approximately 1/n (n is an integer of two or more). The first amplifier is constituted by an odd number of inverter circuits.

Abstract: A plurality of memory macros are laid out in a semiconductor chip. Macro ID generation circuits generate macro IDs for identifying the memory macros, and have different layouts. These macro ID generation circuits are arranged outside the memory macros in the semiconductor chip, so that test control blocks in the memory macros can use the same layouts between all the memory macros to reduce the design load.

Abstract: A semiconductor substrate has a bulk region and a semiconductor region formed either on a buried insulating film or on a cavity region. The bulk region contains a plurality of memory cells, sense amplifiers and column selection gates, while the semiconductor region contains word line selection circuits and column selection circuits.

Abstract: A plurality of wirings are arranged approximately in parallel. A first amplifier is arranged in one wiring of the two adjacent wirings which are included in the plurality of wirings. The first amplifier is arranged at least at a position which divides the interval of a predetermined distance of one wiring by approximately 1/n (n is an integer of two or more). The first amplifier is constituted by an odd number of inverter circuits.

Abstract: An electronic circuit according to this invention includes a first delay compensation circuit which receives a first power supply voltage and a first signal and outputs a first output signal delayed by a first predetermined time, a second delay compensation circuit which receives a second power supply voltage and the first signal and outputs a second output signal delayed by a second predetermined time, a first logic circuit which receives the first power supply voltage and the second output signal output from the second delay compensation circuit and outputs a first operation result by performing first logic operation, and a second logic circuit which receives the second power supply voltage and the first output signal output from the first delay compensation circuit and outputs a second operation result by performing second logic operation.

Abstract: A plurality of basic unit blocks include a memory cell array and first data lines transmitting data read out from memory cell arrays. Second data lines are arranged in an upper layer in a plurality of basic unit blocks. First power supply wirings are arranged along the second data lines. Second power supply wirings are arranged in a direction orthogonal to the first power supply wirings in the upper layer of the basic unit block of the plurality of basic unit blocks which is positioned on one end. The second power supply wirings are arranged in the same layer where the first power supply wirings are formed, and are connected to the first wirings.

Abstract: A semiconductor substrate has a bulk region and a semiconductor region formed either on a buried insulating film or on a cavity region. The bulk region contains a plurality of memory cells, sense amplifiers and column selection gates, while the semiconductor region contains word line selection circuits and column selection circuits.

Abstract: In a semiconductor memory device having a redundant cell array, a replacement control circuit stores in advance a faulty address in an address space assigned to the memory cell array and information for specifying the dimension of the faulty address, compares each of external addresses XA and YA with the stored faulty address, and detects their coincidence. When the external address coincides with the faulty address, a redundant row or a redundant column constituting the redundant cell array is selected and replaced with the faulty cell, on the basis of the information representing the dimension of the faulty address. By this operation, the faulty cell on the memory cell array can be flexibly relieved, and the flexibility of redundancy can be improved.

Abstract: Column select lines for selecting a column in a memory cell array are provided near the memory cell array. Main column select sections including drivers are connected to one end of the column select lines. Latch circuits are connected to the other end of the column select lines. Receiving the output signal from the driver, the latch circuit, together with the driver, drives the column select line.

Abstract: A semiconductor integrated circuit comprises a first internal power supply circuit for producing a first internal supply voltage, a clamp circuit for short-circuiting an output node of the first internal power supply circuit and a first external power supply node, a power-on sensing circuit for, upon detecting a second external supply voltage having reached a specified value, producing a first control signal, a second internal power supply circuit responsive to the second external supply voltage for producing a second internal supply voltage, and a potential detecting circuit for, upon detecting the second internal supply voltage having reached a specified value, producing a second control signal.

Abstract: Where a first bit line pair comprises a first bit line and a second bit line, a first memory cell is located at an intersection between a selected word line and the first bit line. Where a second bit line pair comprises a third bit line and a fourth bit line, a second memory cell is located at an intersection between the selected word line and the fourth bit line. A data line pair comprises a first data line and a second data line. A first column switch comprises a first transistor connected between the first bit line and the first data line and a second transistor connected between the second bit line and the second data line. A second column switch comprises a third transistor connected between the third bit line and the first data line and a fourth transistor connected between the fourth bit line and the second data line.

Abstract: A defective address memory circuit stores the address of a defective data line, and outputs a signal for replacing the defective data line depending on the stored address. Decode circuits constituting a decoder group simultaneously output signals for replacing data lines depending on the output signal from the defective address memory circuit. First and second switch groups shift data lines in the direction of a redundant data line depending on an output signal from the decode circuit to instantaneously replace the defective data line.

Abstract: A semiconductor memory device includes a plurality of memory cell arrays, a plurality of decoders for decoding a first address of memory addresses, each of the decoders being connected to a corresponding memory cell array, and a plurality of sense amplifiers, each connected to a corresponding memory cell array. Also included are a decoder for decoding a second address of the memory addresses, the decoder being connected to every memory cell array, to be shared by every memory cell array, a plurality of redundancy memory cells, each of which is arranged for a corresponding memory cell array, and a plurality of programming circuits, each, arranged relative to a corresponding memory cell array to receive the first memory address and output a signal of a predetermined logic level corresponding to a defective memory cell in a memory cell array.