Abstract: A semiconductor integrated circuit device includes a plurality of sense amplifier line pairs, a plurality of sense amplifier latch circuits respectively connected to the sense amplifier line pairs, and a sense amplifier driver circuit which supplies a sense amplifier activation signal to the sense amplifier latch circuits. The sense amplifier driver circuit is provided for each of the plurality of sense amplifier latch circuits and supplies the sense amplifier activation signal to each of the plurality of sense amplifier latch circuits.

Abstract: A nonvolatile semiconductor memory device includes a nonvolatile storage element to which data is inhibited from being rewritten, a read operation control circuit which captures a read operation instruction signal in synchronization with an external input clock, and a write operation control circuit to which a write operation instruction signal is input asynchronously with the external input clock. The read operation instruction signal gives an instruction to start a read operation to read data out of the nonvolatile storage element, and the write operation instruction signal gives an instruction to start a write operation to write data to the nonvolatile storage element. The device further includes a reset circuit which resets an operation of the read operation control circuit upon receiving the write operation instruction signal.

Abstract: A semiconductor memory device is configured to execute a standby operation for saving power during standby, and comprises a memory cell array including a plurality of memory cells arranged at intersections of bit lines and word lines and operative to store cell data. A redundant memory cell array shares the bit lines with the memory cell array and includes a plurality of redundant memory cells arranged at intersections of the bit lines and redundant word lines and operative to store redundant data for error correction of cell data stored in the memory cell array. A sense amp is operative to sense and amplify the voltage on the bit line to read the cell data or the redundant data from the memory cell array or the redundant memory cell array. A cyclic redundant encoder/decoder is operative to encode the cell data through sequential processing to generate the redundant data or operative to decode the cell data and the redundant data through sequential processing to execute error correction of the cell data.

Abstract: A semiconductor memory device includes a memory element, a first data line and a second data line, a first selection transistor, and a second selection transistor. The memory element includes a semiconductor element of MOS structure in which data is programmed when an insulating film provided in the semiconductor element is broken down by application of a voltage thereto. The first and second data lines are connected to a sense amplifier. The first selection transistor is configured to connect the memory element to the first data line in order to program data in the memory element. The second selection transistor is configured to connect the memory element to the second data line in order to program data in the memory element and detect the data programmed in the memory element. The second selection transistor has a smaller gate-electrode width smaller than the first selection transistor.

Abstract: A nonvolatile semiconductor memory device comprising a storage element which is programmed with information by varying electrical properties irreversibly, a selection switch connected in series to the storage element, a protection element connected in parallel to the storage element to protect the storage element from irreversible variations of electrical properties when the storage element is unprogrammed, a first activation circuit which activates the selection switch, a second activation circuit which activates the protection element in complement with the first activation circuit in normal mode, and a test circuit which conducts a test on the storage element while the second activation circuit is activating the protection element together with the first activation circuit in test mode.

Abstract: A semiconductor device includes a three or more-stage semiconductor charge pump. The capacitance of a pumping capacitor that increases and decreases the potential of a final-stage node on the output side is larger than that of a pumping capacitor that increases and decreases the potential of another-stage node.

Abstract: A semiconductor device has a MOS capacitor in which a drain region and a source region of a MOS structure are commonly connected, and a capacitance is formed between the commonly connected drain region/source region and a gate electrode of the MOS structure; and a wiring capacitor which has a first comb-shaped wiring that is formed on said MOS capacitor through an interlayer insulating film, is connected to the gate electrode of said MOS capacitor, and has projecting portions projecting like comb teeth and a second comb-shaped wiring that is formed on said MOS capacitor through the interlayer insulating film, is arranged across an inter-line insulating film from the first comb-shaped wiring, is connected to the drain region and source region, and has projecting portions projecting like comb teeth, wherein the projecting portions of the second comb-shaped wiring are arranged alternately with the projecting portions of the first comb-shaped wiring and arranged perpendicularly to a channel direction connecting t

Abstract: A semiconductor charge pump includes a plurality of P-channel MOS transistors being connected in series, a plurality of first pumping capacitors one electrode of each of which is connected to a connection point of each of the P-channel MOS transistors, a clock signal generating circuit which generates first and second clock signals whose phases are different from each other by 180 degrees, the first and second clock signals being alternately supplied to the other electrodes of the first pumping capacitors. The semiconductor charge pump further includes a plurality of dynamic level converter circuits each including a resistor element and a second pumping capacitor and connected to each of gates of the P-channel MOS transistors.

Abstract: A semiconductor integrated circuit device includes a storage unit arranged on a semiconductor chip to store a plurality of data, and a plurality of registers provided on the semiconductor chip, the registers storing the data transferred from the storage unit, respectively. The storage unit has a nonvolatile memory element section and a volatile memory element section. The nonvolatile memory element section includes an address area which stores identification information of the registers as addresses and a data area which stores the data to correspond to the addresses by varying electrical characteristics irreversibly. The volatile memory element section temporarily stores the data read from the nonvolatile memory element section.

Abstract: A semiconductor memory device includes a memory cell array comprising a plurality of memory sub-array blocks arranged in a row direction, a plurality of sub-word lines which extend in the row direction to connect with the plurality of memory cells, a plurality of sub-word-line drivers, a plurality of sub-word-line level shifters, a first pre-decoded line group which is connected with the respective sub-word-line drivers, a second pre-decoded line group which extends across the memory sub-array block in the row direction and is connected with the sub-word-line level shifters, and a pre-row-decoder which supplies information of a selected cell to the first and second pre-decoded lines.

Abstract: A nonvolatile semiconductor memory device includes a storage element which is programmed with information by breaking an insulating film by application of electrical stress to the storage element, a control switch which controls the application of electrical stress to the storage element, and a control circuit which controls conduction/nonconduction of the control switch. The device further includes a power supply circuit including a voltage generation circuit which generates a first voltage to cause the electrical stress in program operation, a sensing circuit which senses that the insulating film is broken down, and a counter circuit which controls the control circuit to interrupt the application of electrical stress to the storage element when a given period of time elapses after the sensing circuit senses that the insulating film is broken down.

Abstract: A nonvolatile semiconductor memory device having a storage element which is programmed with information by breaking an insulating film of the storage element, includes a cell array including a plurality of storage cells arranged in matrix, each of the storage cells having the storage element and a selection switch connected in series to the storage element, and a row selection control circuit which activates a row selection line connected to a given number of storage cells. The device further includes a write control circuit which controls a voltage of each of data lines bit by bit in accordance with write data, the data lines being connected to a given number of storage cells connected to the row selection line activated by the row selection control circuit.

Abstract: A nonvolatile semiconductor memory device comprising a storage element which is programmed with information by varying electrical properties irreversibly, a selection switch connected in series to the storage element, a protection element connected in parallel to the storage element to protect the storage element from irreversible variations of electrical properties when the storage element is unprogrammed, a first activation circuit which activates the selection switch, a second activation circuit which activates the protection element in complement with the first activation circuit in normal mode, and a test circuit which conducts a test on the storage element while the second activation circuit is activating the protection element together with the first activation circuit in test mode.

Abstract: A multiplexer circuit is composed of several basic unit circuits, which are each supplied with a data signal and select signal. Each output terminal of several basic unit circuits is connected to a common line. Each basic unit circuit is composed of an unmatch detection circuit detecting an unmatch state of the common line and the data signal, a control circuit controlling drive timing of the common line when receiving a state transition of the select signal, and a tri-state buffer driving the common line according to a state of the data signal when an output of the unmatch detection circuit and an output of the control circuit are both in an active state while holds high impedance state when the state other than above is given.

Abstract: A semiconductor substrate has a bulk region and a semiconductor region formed either on a buried insulating film or on a cavity region. The bulk region contains a plurality of memory cells, sense amplifiers and column selection gates, while the semiconductor region contains word line selection circuits and column selection circuits.

Abstract: A semiconductor integrated circuit device includes a storage element, state sensing circuit, and control circuit. Information is programmed in the storage element by electrically irreversibly changing the element characteristics. The state sensing circuit is configured to sense the irreversibly changed state of the storage element in distinction from an unchanged state. The control circuit is configured to change the sensibility of the state sensing circuit.

Abstract: A semiconductor device includes a three or more-stage semiconductor charge pump. The capacitance of a pumping capacitor that increases and decreases the potential of a final-stage node on the output side is larger than that of a pumping capacitor that increases and decreases the potential of another-stage node.

Abstract: A semiconductor memory device includes a memory cell array comprising a plurality of memory sub-array blocks arranged in a row direction, a plurality of sub-word lines which extend in the row direction to connect with the plurality of memory cells, a plurality of sub-word-line drivers, a plurality of sub-word-line level shifters, a first pre-decoded line group which is connected with the respective sub-word-line drivers, a second pre-decoded line group which extends across the memory sub-array block in the row direction and is connected with the sub-word-line level shifters, and a pre-row-decoder which supplies information of a selected cell to the first and second pre-decoded lines.

Abstract: A semiconductor integrated circuit device includes a data memory which stores write data, a holding circuit which holds the write data, a data write circuit which, during a write operation in a normal mode, supplies the write data held in the holding circuit to the data memory, and, during a write operation in a testing mode, inverts or does not invert the write data held in the holding circuit in accordance with an inversion control signal having a frequency substantially equal to a frequency of the write operation in the normal mode, and supplies the data to the data memory, and a data read circuit which outputs readout data from the data memory.

Abstract: A semiconductor integrated circuit device includes a storage element, state sensing circuit, and control circuit. Information is programmed in the storage element by electrically irreversibly changing the element characteristics. The state sensing circuit is configured to sense the irreversibly changed state of the storage element in distinction from an unchanged state. The control circuit is configured to change the sensibility of the state sensing circuit.