Patents by Inventor Toshinari Takayanagi
Toshinari Takayanagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11079831Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.Type: GrantFiled: March 25, 2019Date of Patent: August 3, 2021Assignee: Apple Inc.Inventors: Toshinari Takayanagi, Jung Wook Cho, Patrick D. McNamara
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Patent number: 10859628Abstract: An apparatus includes a functional circuit, including a power supply node, and a test circuit. The functional circuit is configured to operate in a test mode that includes generating respective test output patterns in response to application of a plurality of test stimulus patterns. The test circuit is configured to identify a particular test stimulus pattern of the plurality of test stimulus patterns, and to reapply the particular test stimulus pattern to the functional circuit multiple times. The test circuit is further configured to vary, for each reapplication, a start time of the particular test stimulus pattern in relation to when a voltage level of the power supply node is sampled for that reapplication.Type: GrantFiled: April 4, 2019Date of Patent: December 8, 2020Assignee: Apple Ine.Inventors: Bibo Li, Bo Yang, Vijay M. Bettada, Matthias Knoth, Toshinari Takayanagi
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Publication number: 20200319248Abstract: An apparatus includes a functional circuit, including a power supply node, and a test circuit. The functional circuit is configured to operate in a test mode that includes generating respective test output patterns in response to application of a plurality of test stimulus patterns. The test circuit is configured to identify a particular test stimulus pattern of the plurality of test stimulus patterns, and to reapply the particular test stimulus pattern to the functional circuit multiple times. The test circuit is further configured to vary, for each reapplication, a start time of the particular test stimulus pattern in relation to when a voltage level of the power supply node is sampled for that reapplication.Type: ApplicationFiled: April 4, 2019Publication date: October 8, 2020Inventors: Bibo Li, Bo Yang, Vijay M. Bettada, Matthias Knoth, Toshinari Takayanagi
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Publication number: 20190286210Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.Type: ApplicationFiled: March 25, 2019Publication date: September 19, 2019Inventors: Toshinari Takayanagi, Jung Wook Cho, Patrick D. McNamara
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Patent number: 10241560Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.Type: GrantFiled: July 18, 2016Date of Patent: March 26, 2019Assignee: Apple Inc.Inventors: Toshinari Takayanagi, Jung Wook Cho, Patrick D. McNamara
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Patent number: 10054618Abstract: In an embodiment, an integrated circuit includes a first circuit and a characterization circuit to capture a histogram of the supply voltage magnitude to the first circuit (or other characteristics of the first circuit). In various embodiments, the characterization circuit may: be located near the first circuit; include a sample/hold circuit that may sample the supply voltage in a short window of time and an ADC that is configured to converge to the sampled voltage over multiple orders of magnitude longer than the short window; be relatively small and low power; capture multiple histograms, e.g. one for each mode of the first circuit; support a blackout interval during mode changes; support a zoom feature to a subrange of supply voltage disabled with fine-grain histogram buckets; and/or include one or more comparators to detect maximum and/or minimum voltages experienced over a time interval.Type: GrantFiled: August 18, 2015Date of Patent: August 21, 2018Assignee: Apple Inc.Inventors: Matthias Knoth, Conrad H. Ziesler, Toshinari Takayanagi
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Patent number: 10001800Abstract: Techniques are disclosed relating to power management of an integrated circuit. In one embodiment, an integrated circuit includes a plurality of temperature sensors configured to measure a plurality of temperatures at different locations in the integrated circuit. The integrated circuit further includes a power management circuit configured to determine a set of guard bands based on a temperature difference determined using the plurality of temperatures. The power management circuit is configured to adjust, using the set of guard bands, a particular one of the plurality of temperatures, and to use the adjusted particular temperature to manage power consumption of the integrated circuit. In some embodiments, the power management circuit is configured to manage the power consumption by adjusting a voltage supplied to the integrated circuit, the adjusted voltage being based on the adjusted particular temperature.Type: GrantFiled: September 10, 2015Date of Patent: June 19, 2018Assignee: Apple Inc.Inventors: Toshinari Takayanagi, Yizhang Yang
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Publication number: 20170052219Abstract: In an embodiment, an integrated circuit includes a first circuit and a characterization circuit to capture a histogram of the supply voltage magnitude to the first circuit (or other characteristics of the first circuit). In various embodiments, the characterization circuit may: be located near the first circuit; include a sample/hold circuit that may sample the supply voltage in a short window of time and an ADC that is configured to converge to the sampled voltage over multiple orders of magnitude longer than the short window; be relatively small and low power; capture multiple histograms, e.g. one for each mode of the first circuit; support a blackout interval during mode changes; support a zoom feature to a subrange of supply voltage disabled with fine-grain histogram buckets; and/or include one or more comparators to detect maximum and/or minimum voltages experienced over a time interval.Type: ApplicationFiled: August 18, 2015Publication date: February 23, 2017Inventors: Matthias Knoth, Conrad H. Ziesler, Toshinari Takayanagi
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Publication number: 20170010646Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.Type: ApplicationFiled: July 18, 2016Publication date: January 12, 2017Inventors: Toshinari Takayanagi, Jung Wook Cho, Patrick D. McNamara
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Patent number: 9395775Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.Type: GrantFiled: June 25, 2013Date of Patent: July 19, 2016Assignee: Apple Inc.Inventors: Toshinari Takayanagi, Jung Wook Cho, Patrick D. McNamara
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Patent number: 9337825Abstract: A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.Type: GrantFiled: June 19, 2014Date of Patent: May 10, 2016Assignee: Apple Inc.Inventors: Toshinari Takayanagi, Shingo Suzuki
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Patent number: 9294103Abstract: A method and apparatus for achieving fast PLL lock when exiting a low power state is disclosed. In one embodiment, a method includes operating a PLL in a first state in which the PLL is locked to a first frequency. The method further includes programming the PLL to operate in a second state in which the PLL is locked to a second frequency. The programming may occur while the PLL is operating in the first state, and the PLL may continue operating in the first state after programming is complete. Thereafter, the PLL may be transitioned from the first state to a low power state. Upon exiting the low power state, the PLL may transition directly to the second state, locking to the second frequency, without having to transition to the first state or lock to the first frequency.Type: GrantFiled: February 14, 2014Date of Patent: March 22, 2016Assignee: Apple Inc.Inventors: Jong-Suk Lee, Shih-Chieh R. Wen, Toshinari Takayanagi, Wei-Han Lien
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Publication number: 20150236705Abstract: A method and apparatus for achieving fast PLL lock when exiting a low power state is disclosed. In one embodiment, a method includes operating a PLL in a first state in which the PLL is locked to a first frequency. The method further includes programming the PLL to operate in a second state in which the PLL is locked to a second frequency. The programming may occur while the PLL is operating in the first state, and the PLL may continue operating in the first state after programming is complete. Thereafter, the PLL may be transitioned from the first state to a low power state. Upon exiting the low power state, the PLL may transition directly to the second state, locking to the second frequency, without having to transition to the first state or lock to the first frequency.Type: ApplicationFiled: February 14, 2014Publication date: August 20, 2015Applicant: APPLE INC.Inventors: Jong-Suk Lee, Shih-Chieh R. Wen, Toshinari Takayanagi, Wei-Han Lien
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Patent number: 8970234Abstract: A method and apparatus for temperature sensor calibration is disclosed. In one embodiment, an integrated circuit (IC) is tested at a first known temperature corresponding to a first temperature threshold. During the test, a first temperature reading is obtained from a temperature sensor. A first offset is calculated by determining the difference between the first known temperature and the first temperature reading. The first offset is recorded in a storage unit for later use during operation of the IC. During operation, the first offset may be added to temperature readings obtained from a temperature sensing unit to produce an adjusted temperature value. The adjusted temperature value may be compared to one or more temperature thresholds. Based on the comparisons, a power management unit may perform power control actions.Type: GrantFiled: September 26, 2011Date of Patent: March 3, 2015Assignee: Apple Inc.Inventors: Toshinari Takayanagi, Jung Wook Cho
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Patent number: 8959369Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.Type: GrantFiled: January 8, 2014Date of Patent: February 17, 2015Assignee: Apple Inc.Inventors: Josh P. de Cesare, Jung Wook Cho, Toshinari Takayanagi, Timothy J. Millet
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Publication number: 20140380066Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.Type: ApplicationFiled: June 25, 2013Publication date: December 25, 2014Inventors: Toshinari Takayanagi, Jung Wook Cho, Patrick D. McNamara
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Patent number: 8862926Abstract: A system and method for efficiently managing multiple PLLs on a system on a chip (SOC). A SOC includes a hardware phase lock loop (PLL) switching control block coupled to a software interface. The hardware PLL switching (HPS) control block receives PLL switch requests from software. The request identifies a given core clock received by a given processing core of multiple processor cores on the SOC and indicates the identified core clock is not to be provided anymore by a current PLL. The request indicates a given search method including search conditions. The HPS control block searches for a target PLL that satisfies these search conditions. In response to finding the target PLL, the HPS control block changes clock network connections and parameters across the die of the SOC. These changes across the die disconnect the identified core clock from the current PLL and connects the identified core clock to the target PLL.Type: GrantFiled: August 16, 2011Date of Patent: October 14, 2014Assignee: Apple Inc.Inventors: Josh P. de Cesare, Jung Wook Cho, Toshinari Takayanagi
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Publication number: 20140300407Abstract: A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.Type: ApplicationFiled: June 19, 2014Publication date: October 9, 2014Inventors: Toshinari Takayanagi, Shingo Suzuki
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Patent number: 8786309Abstract: A multi-path power switch scheme for functional block wakeup is disclosed. The scheme may be applied to functional blocks of an integrated circuit. When a power on procedure is initiated within a given functional block, a first group of power switches in a functional block may be powered on, while a second group of power switches is inhibited from powering on. After a predetermined time has elapsed, activation of the second group of power switches is initiated. After initiation of a power up procedure for a given functional block, the powering up of a second functional block to be powered on may initially be inhibited. After a predetermined time has elapsed, the powering on of the second functional block may be initiated. Overlap between times when the first and second groups of switches are active may depend on process, voltage, and temperature variations.Type: GrantFiled: October 31, 2011Date of Patent: July 22, 2014Assignee: Apple Inc.Inventors: Toshinari Takayanagi, Shingo Suzuki
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Patent number: 8779836Abstract: A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.Type: GrantFiled: August 21, 2013Date of Patent: July 15, 2014Assignee: Apple Inc.Inventors: Toshinari Takayanagi, Shingo Suzuki