Abstract: CMOS circuitry having mixed threshold voltages is disclosed. Circuits may be implemented using PMOS transistors, NMOS transistors, or both. For at least one given type of transistor (PMOS or NMOS), a circuit includes at least one transistor configured to switch at a first nominal threshold voltage and at least one transistor configured to switch at a second nominal threshold voltage. The different threshold voltages among a given transistor type are realized by varying the thickness of the transistor gate oxides and/or the channel dopant density, for example.

Abstract: In one embodiment, a power gated circuit block includes power switches that couple at least one of the power supply grids within the block to the global power supply grids of the integrated circuit. The power switches receive an enable that indicates whether or not the power gated block is enabled or disabled. If the power gated block is enabled, the power switches are turned on and electrically connect the global power supply grid with the internal (or local) power supply grid; otherwise the power switches electrically isolate the local power supply grid from the global power supply grid. The power switches are physically distributed over an area occupied by the power gated block, including near an edge of the area. The number of power switches near the edge is greater than the number of switches included at other locations in the area to provide a worst case impedance experienced at points throughout the area that is approximately equal.

Abstract: In an embodiment, an integrated circuit comprises a plurality of temperature sensors and a power manager coupled thereto. The temperature sensors are physically distributed over an area of the integrated circuit that is occupied by logic circuitry implementing the operations for which the integrated circuit is designed. The power manager is configured to transmit a power supply voltage request to an external power supply module, the power supply voltage request indicating a requested magnitude of the power supply voltage for the integrated circuit. The power manager is configured to modify the requested magnitude responsive to indications from each of the plurality of temperatures sensors that represent a temperature of the integrated circuit sensed by each of the plurality of temperature sensors.

Abstract: A method is provided for modeling timing characteristics of a circuit block of an integrated circuit, which includes a main circuit and a timing circuit. The method comprises determining an output pin output delay and determining a timing circuit delay. The output pin output delay is an interval of time from a clock signal reaching a clock reference point (CRP) to an output signal arriving at the output pin. The clock reference point is positioned between the timing circuit and the main circuit. The timing circuit delay is an interval of time from a clock signal arriving at a clock input pin to a clock signal arriving at the CRP. The determination of the timing circuit delay is based on a computer simulation of a netlist of circuit elements in the timing circuit.

Abstract: A method for optimizing low threshold-voltage (Vt) devices in an integrated circuit design. The method includes identifying paths and nodes within the integrated circuit design, determining node overlap within the integrated circuit design, calculating possible solutions for addressing timing violations within the integrated circuit design, choosing a solution for addressing timing violations, inserting low Vt devices at particular nodes of the integrated circuit design, and repeating the calculated possible solutions wherein choosing a solution and inserting low Vt devices at particular nodes to address timing violations within the integrated circuit design.

Abstract: An accumulated data-dependent post-manufacture shift in a characteristic of one or more of a pair of matched devices within an integrated circuit may cause a mismatch in the characteristic between the pair of matched devices. This mismatch may be reduced by preconditioning the matched devices to cause an initial shift in the characteristic in each of the matched devices and to thereby reduce an expected magnitude of any further lifetime shift in the characteristic of either matched device. In an exemplary sense amplifier circuit having matched cross-coupled PMOS load devices, a data dependent threshold mismatch between the PMOS devices resulting from a Negative Bias Temperature Instability (NBTI) effect may be reduced by biasing both of the matched PMOS devices so that both experience an initial NBTI Vt shift, and so that any expected further Vt shift in either device over the product lifetime is reduced.

Abstract: A multi-port semiconductor memory device is provided with current limiting transistor devices interposed between the memory cell and the bit line transfer gates for multiple bit line pairs. Where each bit line pair represents a memory port that is connected to the memory cell during read and write operations, the current limiting transistor devices effectively reduce the current flow from non-writing bit lines, thereby improving memory writability. In addition, the current limiting transistor devices effectively reduce the current flow to non-reading bit lines, thereby improving memory stability.

Abstract: A method for optimizing low threshold-voltage (Vt) devices in an integrated circuit design. The method includes identifying paths and nodes within the integrated circuit design, determining node overlap within the integrated circuit design, calculating possible solutions for addressing timing violations within the integrated circuit design, choosing a solution for addressing timing violations, inserting low Vt devices at particular nodes of the integrated circuit design, and repeating the calculated possible solutions wherein choosing a solution and inserting low Vt devices at particular nodes to address timing violations within the integrated circuit design.

Abstract: A system and method for adjusting the clock delay in a self-timed memory system having a memory array and a sense amplifier includes a programmable delay circuit coupled as an input to the sense amplifier for controlling the timing of when the sense amplifier is enabled in relation to the memory array addressing by generating a plurality of delayed versions of the sense amplifier enable signal and coupling one of the delayed versions of the sense amplifier enable signal to the sense amplifier in response to a control signal. By multiplexing multiple delayed versions of the sense amplifier enable signal under control of programmable delay selection logic, an optional delay is provided to make enable the sense amplifier more quickly or more slowly in reference to a memory array signal, depending upon control signal inputs to the selection logic.

Abstract: A system and method for adjusting the clock delay in a self-timed memory system having a memory array and a sense amplifier includes a programmable delay circuit coupled as an input to the sense amplifier for controlling the timing of when the sense amplifier is enabled in relation to the memory array addressing by generating a plurality of delayed versions of the sense amplifier enable signal and coupling one of the delayed versions of the sense amplifier enable signal to the sense amplifier in response to a control signal. By multiplexing multiple delayed versions of the sense amplifier enable signal under control of programmable delay selection logic, an optional delay is provided to make enable the sense amplifier more quickly or more slowly in reference to a memory array signal, depending upon control signal inputs to the selection logic.

Abstract: A multi-port semiconductor memory device is provided with current limiting transistor devices interposed between the memory cell and the bit line transfer gates for multiple bit line pairs. Where each bit line pair represents a memory port that is connected to the memory cell during read and write operations, the current limiting transistor devices effectively reduce the current flow from non-writing bit lines, thereby improving memory writability. In addition, the current limiting transistor devices effectively reduce the current flow to non-reading bit lines, thereby improving memory stability.

Abstract: An adder logic circuit for performing an addition operation of a first numerical value and a second numerical value having a bit width narrower than that of the first numerical value is described.

Abstract: A data transfer circuit includes data lines for transferring data, interface input/output blocks connected to the data lines for input or output of data through the data lines, and a leakage current monitor and compensate circuit connected to the data lines to detect and store magnitudes of leakage currents in the data lines before input or output of data, and generate and supply to the data lines compensation currents that compensate the leakage currents upon input or output of data. An example of the data line is a bit line of a memory, and an example of the interface input/output block is a memory cell.

Abstract: A method and apparatus for bypassing defective cache memory locations on-board a microprocessor integrated circuit chip, which includes a processor, a cache memory, a store buffer, a tag RAM, and a comparator. The cache memory has a plurality of valid cache memory locations and at least one defective cache memory location. The store buffer has buffer entries and redundancy entries for storing data sent by the processor for storage in the cache memory. The tag RAM has buffer tag entries for storing addresses of data stored in the buffer entries and redundancy tag entries that store addresses of defective cache memory locations in the cache memory. The comparator compares addresses of data sent by the processor for cache memory storage with addresses stored in the redundancy tag entries.

Abstract: A data transfer circuit includes data lines for transferring data, interface input/output blocks connected to the data lines for input or output of data through the data lines, and a leakage current monitor and compensate circuit connected to the data lines to detect and store magnitudes of leakage currents in the data lines before input or output of data, and generate and supply to the data lines compensation currents that compensate the leakage currents upon input or output of data. An example of the data line is a bit line of a memory, and an example of the interface input/output block is a memory cell.

Abstract: A semiconductor memory includes a memory cell including inverters (IN1, IN2), control transistors (T3, T4) that control the potential of a ground side terminal (N3) connected to the memory cell, and transfer transistors T1 and T2 that control transfer of data from bit lines (BL, /BL) to the memory cell. In writing data, the control transistors raise the potential of the ground side terminal (N3) to be higher than the ground potential by a predetermined potential. After the transfer transistors transfer data having a potential difference smaller than a potential difference between the power supply potential and the ground potential from the bit lines (BL, /BL) to the memory cell, and cause the memory cell to hold the data, the potential of the ground side terminal (N3) is decreased to the ground potential to write data.

Abstract: A cache memory employs a set-associative method for associating cached data with main storage data. The cache memory comprises memory cells MSs, sense amplifiers SAW0 through SAWs-1, s way hit signal generators 1-0 through 1-s-1 for searching directories of address tags of respective ways for a given tag and generating way hit signals W0HIT through Ws-1HIT accordingly, and controllers 3-1 through 3-s-1 for activating a sense amplifier SAWi corresponding to a hit way according to the way hit signals WiHIT, keeping the other sense amplifiers SAWj (j is not equal to i) inactive, and keeping all of the sense amplifiers SAWk (k=1, . . . , s) OFF when a cache miss is detected.

Abstract: The associative memory capable of improving the efficiency in replacing an entry and testability of compare operation. The associative memory includes a Content Addressable Memory (CAM) cell array for executing a compare operation; a Random Access Memory (RAM) cell array for operating responsive to a result of the CAM cell array; and a HIT entry number detection circuit for receiving a result of the compare operation in the CAM cell array and outputting a HIT entry number.

Abstract: A logical circuit includes an inverter circuit for judging fluctuations of a potential at a potential detecting point, a power-source potential step-down circuit for supplying a potential between a potential at a switching point of the inverter circuit and a high-level power-source potential, from an output end thereof, a MOS transistor of P-channel for controlling in conductivity a location between the output end of the power-source potential step-down circuit and the potential detecting point, and a group of MOS transistors of N-channel for controlling in conductivity a location between the potential detecting point and a ground power source in accordance with an input signal.

Abstract: The invention relates to a multi-port memory, wherein data is written into, and read from, a memory cell in multi-port scheme. The memory is designed to solve the problem that the data-writing speed decreases when data-writing and data-reading with respect to the same memory cell conflict with each other. To solve the problem, when data-writing and data-reading with respect to the same memory cell (102) conflict with each other, a bit-line load control circuit (130) is connected, in accordance with address signals and write-enable signals, to bit lines (BLa, /BLa, BLb, /BLb) for selecting the memory cell (102) and turns off bit-line load circuits (117, 127) for supplying a predetermined potential to the bit lines (BLa, /BLa, BLb, /BLb), thereby preventing the data-reading speed from decreasing.