Patents by Inventor Toshio Fujisawa
Toshio Fujisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220066921Abstract: According to one embodiment, a nonvolatile memory includes a memory chip and a command processing unit. The command processing unit stores data read from a first position of the memory chip in a memory when a first command for compaction is received from a controller, transmits validity determination information used for determining whether or not the data read from the first position is valid to the controller, and writes valid data of the data stored in the memory to a second position of the memory chip when a second command for the compaction and validity identification information that identifies the valid data are received from the controller.Type: ApplicationFiled: February 24, 2021Publication date: March 3, 2022Inventors: Daisuke IWAI, Toshio FUJISAWA, Keigo HARA
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Publication number: 20220011963Abstract: A memory system has a memory, a first substrate on which the memory is mounted and which is set to a temperature of ?40[° C.] or lower, a controller configured to control the memory; and a second substrate on which the controller is mounted, which is set to a temperature of ?40[° C.] or higher, and which transmits and receives a signal to and from the first substrate via a signal transmission cable.Type: ApplicationFiled: March 10, 2021Publication date: January 13, 2022Applicant: Kioxia CorporationInventors: Tomoya SANUKI, Yuta AIBA, Hitomi TANAKA, Masayuki MIURA, Mie MATSUO, Toshio FUJISAWA, Takashi MAEDA
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Publication number: 20210272946Abstract: A semiconductor storage device includes a plurality of memory chips and a circuit chip. The plurality of memory chips and the circuit chip are stacked on each other. Each of the plurality of memory chips has a memory cell array that includes a plurality of memory cells. The circuit chip includes a data latch configured to store page data for writing or reading data into or from the memory cell array of each of the memory chips.Type: ApplicationFiled: August 28, 2020Publication date: September 2, 2021Inventors: Tomoya SANUKI, Toshio FUJISAWA, Hiroshi MAEJIMA, Takashi MAEDA
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Publication number: 20210149568Abstract: According to one embodiment, a storage device includes a stage on which a semiconductor wafer can be mounted, wherein data is capable of being read from the semiconductor wafer or data is capable of being written to the semiconductor wafer. The storage device further includes a plurality of probe pins for reading or writing data, and a controller connected the probe pins. The semiconductor wafer includes electrodes connectable to the probe pins, a first memory area that can store user data, and a second memory area that can store identification information for identification of the semiconductor wafer and a check code for checking integrity of the identification information. The controller is capable of reading the identification information and the check code from the second memory area.Type: ApplicationFiled: December 14, 2020Publication date: May 20, 2021Applicant: Kioxia CorporationInventors: Yasuhito YOSHIMIZU, Takashi FUKUSHIMA, Tatsuro HITOMI, Arata INOUE, Masayuki MIURA, Shinichi KANNO, Toshio FUJISAWA, Keisuke NAKATSUKA, Tomoya SANUKI
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Publication number: 20210141746Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.Type: ApplicationFiled: January 22, 2021Publication date: May 13, 2021Inventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
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Patent number: 10929315Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.Type: GrantFiled: June 29, 2018Date of Patent: February 23, 2021Assignee: Toshiba Memory CorporationInventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
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Patent number: 10467020Abstract: According to one embodiment, the memory device includes a non-volatile memory, a volatile memory, and a controller. The controller carries out the transition to two different sleep states depending on a sleep instruction from the host device and saves sleep state information indicating the sleep state after the transition to the host-side storage device. Upon receiving a return instruction from the host device, the controller carries out return processing in accordance with the sleep state information stored in the host-side storage device.Type: GrantFiled: September 2, 2016Date of Patent: November 5, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuji Izumi, Kenichi Maeda, Kenji Funaoka, Reina Nishino, Toshio Fujisawa, Nobuhiro Kondo
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Patent number: 10146483Abstract: According to one embodiment, a memory system is connectable to a host including a first memory. The memory system includes a non-volatile second memory, a volatile third memory, and a controller. The controller uses the third memory as a work memory, and executes data transfer between the host and the second memory. The controller receives a first command to change a power mode from the host. The controller transfers first data to the first memory and transfers second data to the second memory in response to the receipt of the first command. The controller transmits a response of completion of data transfer. The first data and the second data are included in third data. The third data is data in the third memory.Type: GrantFiled: September 1, 2016Date of Patent: December 4, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Reina Nishino, Kenichi Maeda, Kenji Funaoka, Nobuhiro Kondo, Toshio Fujisawa
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Publication number: 20180307632Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.Type: ApplicationFiled: June 29, 2018Publication date: October 25, 2018Inventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
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Patent number: 10061515Abstract: According to one embodiment, an information processing apparatus includes a host and a memory system. The host includes a main memory. The memory system includes a memory access unit and an interface unit. The memory access unit converts a first request into transmission information. The first request is a request for data transfer toward a memory region as a part of the main memory. The interface unit transmits transmission information according to an instruction from the memory access unit.Type: GrantFiled: March 4, 2015Date of Patent: August 28, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masanori Yamato, Shigenori Sugimoto, Toshio Fujisawa, Naoto Oshiyama
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Patent number: 10042786Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.Type: GrantFiled: July 24, 2015Date of Patent: August 7, 2018Assignee: Toshiba Memory CorporationInventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
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Publication number: 20170249247Abstract: According to one embodiment, a memory system is connectable to a host including a first memory. The memory system includes a non-volatile second memory, a volatile third memory, and a controller. The controller uses the third memory as a work memory, and executes data transfer between the host and the second memory. The controller receives a first command to change a power mode from the host. The controller transfers first data to the first memory and transfers second data to the second memory in response to the receipt of the first command. The controller transmits a response of completion of data transfer. The first data and the second data are included in third data. The third data is data in the third memory.Type: ApplicationFiled: September 1, 2016Publication date: August 31, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Reina NISHINO, Kenichi MAEDA, Kenji FUNAOKA, Nobuhiro KONDO, Toshio FUJISAWA
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Publication number: 20170249102Abstract: According to one embodiment, an information processing apparatus includes a host device, a memory system and a power supply circuit. The host device includes a volatile first memory and a first control circuit. The memory system includes a non-volatile second memory in which user data is stored and a second control circuit. The second control circuit executes transfer of the user data between the host device and the second memory. The first memory includes an area used by the second control circuit. The second control circuit uses the area as a buffer for the transfer. The first control circuit causes the power supply circuit to start and stop the power supply to the memory system. The first control circuit accesses, while the power supply to the memory system is stopped, the buffer.Type: ApplicationFiled: September 7, 2016Publication date: August 31, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Kenichi MAEDA, Kenji FUNAOKA, Reina NISHINO, Nobuhiro KONDO, Toshio FUJISAWA
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Publication number: 20170249167Abstract: According to one embodiment, the memory device includes a non-volatile memory, a volatile memory, and a controller. The controller carries out the transition to two different sleep states depending on a sleep instruction from the host device and saves sleep state information indicating the sleep state after the transition to the host-side storage device. Upon receiving a return instruction from the host device, the controller carries out return processing in accordance with the sleep state information stored in the host-side storage device.Type: ApplicationFiled: September 2, 2016Publication date: August 31, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Yuji IZUMI, Kenichi MAEDA, Kenji FUNAOKA, Reina NISHINO, Toshio FUJISAWA, Nobuhiro KONDO
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Interface circuit executing protocol control in compliance with first and second interface standards
Patent number: 9720866Abstract: According to one embodiment, a first module is responsible for protocol control in compliance with a first interface standard. A second module is provided separately from the first module and is responsible for protocol control in compliance with a second interface standard. A third module is responsible for a physical layer shared between the first interface standard and the second interface standard.Type: GrantFiled: March 13, 2015Date of Patent: August 1, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Ken Hamada, Toshio Fujisawa, Nobuhiro Kondo -
Publication number: 20160267027Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.Type: ApplicationFiled: July 24, 2015Publication date: September 15, 2016Inventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
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Patent number: 9396141Abstract: According to embodiments a memory system is connectable to a host which includes a host controller and a host memory including a first memory area and a second memory area. The memory system includes an interface unit, a non-volatile memory, and a controller unit. The interface unit receives a read command and a write command. The controller unit writes write-data to the non-volatile memory according to the write command. The controller unit determines whether read-data requested by the read command is in the first memory area. If the read-data is in the first memory area, the controller unit causes the host controller to copy the read-data from the first memory area to the second memory area. If the read-data is not in the first memory area, the controller unit reads the read-data from the non-volatile memory and causes the host controller to store the read-data in the second memory area.Type: GrantFiled: March 7, 2014Date of Patent: July 19, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Kenichi Maeda, Nobuhiro Kondo, Kenichiro Yoshii, Keigo Hara, Toshio Fujisawa
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Publication number: 20160077994Abstract: According to one embodiment, a first module is responsible for protocol control in compliance with a first interface standard. A second module is provided separately from the first module and is responsible for protocol control in compliance with a second interface standard. A third module is responsible for a physical layer shared between the first interface standard and the second interface standard.Type: ApplicationFiled: March 13, 2015Publication date: March 17, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Ken Hamada, Toshio Fujisawa, Nobuhiro Kondo
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Publication number: 20160077737Abstract: According to one embodiment, an information processing apparatus includes a host and a memory system. The host includes a main memory. The memory system includes a memory access unit and an interface unit. The memory access unit converts a first request into transmission information. The first request is a request for data transfer toward a memory region as a part of the main memory. The interface unit transmits transmission information according to an instruction from the memory access unit.Type: ApplicationFiled: March 4, 2015Publication date: March 17, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Masanori YAMATO, Shigenori Sugimoto, Toshio Fujisawa, Naoto Oshiyama
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Publication number: 20150046634Abstract: According to embodiments a memory system is connectable to a host which includes a host controller and a host memory including a first memory area and a second memory area. The memory system includes an interface unit, a non-volatile memory, and a controller unit. The interface unit receives a read command and a write command. The controller unit writes write-data to the non-volatile memory according to the write command. The controller unit determines whether read-data requested by the read command is in the first memory area. If the read-data is in the first memory area, the controller unit causes the host controller to copy the read-data from the first memory area to the second memory area. If the read-data is not in the first memory area, the controller unit reads the read-data from the non-volatile memory and causes the host controller to store the read-data in the second memory area.Type: ApplicationFiled: March 7, 2014Publication date: February 12, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Kenichi MAEDA, Nobuhiro Kondo, Kenichiro Yoshii, Keigo Hara, Toshio Fujisawa