Abstract: According to one embodiment, a semiconductor memory device includes a plurality of blocks. The blocks includes a first selection transistor, a second selection transistor, a plurality of memory cell transistors, a first selection gate line and a second selection gate line, and word lines. One of the blocks holds information on a word line, a first selection gate line and/or a second selection gate line including a short-circuiting defect.

Abstract: According to one embodiment, a semiconductor memory device includes memory cell arrays each including blocks. The block is unit of erase and includes string-groups. Each string-group includes strings each including a first transistor, memory cell transistors, a second transistor coupled in series. The first transistor is connected to different bit line and the second transistor is connected to same source line. The memory cell arrays are provided with different respective block address signals. The memory cell arrays are provided with different respective string address signals. Each of the block address signals specifies one block. Each of the string address signals specifies one string-group.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of blocks. The blocks includes a first selection transistor, a second selection transistor, a plurality of memory cell transistors, a first selection gate line and a second selection gate line, and word lines. One of the blocks holds information on a word line, a first selection gate line and/or a second selection gate line including a short-circuiting defect.

Abstract: According to one embodiment, a semiconductor memory device includes memory cell arrays each including blocks. The block is unit of erase and includes string-groups. Each string-group includes strings each including a first transistor, memory cell transistors, a second transistor coupled in series. The first transistor is connected to different bit line and the second transistor is connected to same source line. The memory cell arrays are provided with different respective block address signals. The memory cell arrays are provided with different respective string address signals. Each of the block address signals specifies one block. Each of the string address signals specifies one string-group.

Abstract: A semiconductor integrated circuit according to an embodiment includes a clock signal generation section, a clock waveform shaping section and a plurality of function blocks. The clock signal generation section generates a clock signal of a predetermined frequency. The clock waveform shaping section generates a plurality of clock signals having the same phase as a phase of the clock signal generated by the clock signal generation section at rising edges and different phases at falling edges. Each of the plurality of function blocks has a plurality of flip flops that operate with any one of the plurality of clock signals generated by the clock waveform shaping section.

Abstract: A cache memory control circuit includes a selecting section configured to select each way or two or more ways in a cache memory in which plural ways have been divided by a predetermined division number, in a predetermined order; a detecting section configured to detect a cache hit in each way; a controlling section configured to, if the cache hit is detected, stop the selection of each way in the selecting section; and a division number changing section having a comparing section, which compares respective values of two pieces of read data from the cache memory having been propagated through two paths, one of which has a predetermined amount of delay with respect to the other one, the division number changing section which changes the predetermined division number depending on whether the two pieces of the read data match or mismatch with each other in the comparing section.

Abstract: A semiconductor integrated circuit according to an embodiment includes a clock signal generation section, a clock waveform shaping section and a plurality of function blocks. The clock signal generation section generates a clock signal of a predetermined frequency. The clock waveform shaping section generates a plurality of clock signals having the same phase as a phase of the clock signal generated by the clock signal generation section at rising edges and different phases at falling edges. Each of the plurality of function blocks has a plurality of flip flops that operate with any one of the plurality of clock signals generated by the clock waveform shaping section.

Abstract: A cache memory control circuit includes a selecting section configured to be capable of selecting, in a predetermined order, each way or a predetermined two or more ways of a cache memory having multiple ways; a comparing section configured to detect a cache hit in each way; and a control section configured to, upon detection of a cache hit, stop a selection of the respective ways or the predetermined two or more ways at the selecting section.

Abstract: A clock distribution circuit includes a monitoring circuit that delays a signal based on a clock signal from a clock tree by using multiple inverter circuits and predicts a timing violation on the basis of the amount of delay produced by the multiple inverter circuits. The clock distribution circuit further includes an OR circuit that controls, on the basis of the result of prediction by the monitoring circuit, a clock gating signal generated by a combinational circuit and a clock gating circuit that supplies a clock signal or stops supply of the clock signal depending on a signal output from the OR circuit.

Abstract: A digital signal processing device includes: a memory for coefficient storage including partial memories that dividedly store, for each plurality of bits, a plurality of filter coefficients as divided data; a control unit that outputs, to the memory for coefficient storage, an address signal added with activation/inactivation control information; a CE-signal interrupting unit that transmits the CE signals to the partial memories or interrupts the CE signals based on the activation/inactivation control information; an output selecting unit that is provided in at least a part of the partial memories and selects and outputs, based on the activation/inactivation control information, an output of the partial memory or all-bit zero value; a multiplier that performs multiplication of each of a plurality of input data and each of the filter coefficients including the output of the output selecting unit; and an integration circuit system that integrates multiplication results output from the multiplier.

Abstract: A cache memory control circuit includes a selecting section configured to select each way or two or more ways in a cache memory in which plural ways have been divided by a predetermined division number, in a predetermined order; a detecting section configured to detect a cache hit in each way; a controlling section configured to, if the cache hit is detected, stop the selection of each way in the selecting section; and a division number changing section having a comparing section, which compares respective values of two pieces of read data from the cache memory having been propagated through two paths, one of which has a predetermined amount of delay with respect to the other one, the division number changing section which changes the predetermined division number depending on whether the two pieces of the read data match or mismatch with each other in the comparing section.

Abstract: A cache memory control circuit includes a selecting section configured to be capable of selecting, in a predetermined order, each way or a predetermined two or more ways of a cache memory having multiple ways; a comparing section configured to detect a cache hit in each way; and a control section configured to, upon detection of a cache hit, stop a selection of the respective ways or the predetermined two or more ways at the selecting section.

Abstract: A clock distribution circuit includes a monitoring circuit that delays a signal based on a clock signal from a clock tree by using multiple inverter circuits and predicts a timing violation on the basis of the amount of delay produced by the multiple inverter circuits. The clock distribution circuit further includes an OR circuit that controls, on the basis of the result of prediction by the monitoring circuit, a clock gating signal generated by a combinational circuit and a clock gating circuit that supplies a clock signal or stops supply of the clock signal depending on a signal output from the OR circuit.

Abstract: The demodulation unit demodulates a received signal. The detection circuit detects the final data contained in a received data stream supplied from the demodulation unit. When detecting the final data, the detection circuit outputs the final data notification signal. The standby period timer sets the standby time in accordance with the final data notification signal output from the detection circuit.

Abstract: ATM cells inputted into a physical layer interface (12) are once stored in a cell buffer (24) regardless whether they are ATM cells to be outputted from a switching interface (22) or ATM cells addressed to host CPU (26), and the ATM cells addressed to the host CPU are stored in a temporary RAM (18) at a timing controlled by a scheduler (16). The host CPU 26 read out ATM cells stored in the temporary RAM (18) when necessary. Thereby, no FIFO memory is needed to temporarily store ATM cells addressed to the host CPU (26).

Abstract: The demodulation unit demodulates a received signal. The detection circuit detects the final data contained in a received data stream supplied from the demodulation unit. When detecting the final data, the detection circuit outputs the final data notification signal. The standby period timer sets the standby time in accordance with the final data notification signal output from the detection circuit.

Abstract: A storage means control apparatus of this invention includes a first processing unit for performing write processing in a first storage unit, a second processing unit for performing write processing in a second storage unit, a tag data control unit for managing tag data representing storage areas where the first processing unit has performed write processing in the first storage unit (101), another tag data control unit for managing another tag data representing storage areas where the second processing unit has performed write processing in the second storage unit, a priority data control unit for managing priority data representing a priority of each of the first and second processing units in units of storage areas of the second storage unit, a prevention data control unit for managing prevention data for preventing write processing in each storage area of the second storage unit using the priority data and the tag data, and a processing data updating unit for writing the data written in the first storage

Abstract: A storage means control apparatus of this invention includes a first processing unit for performing write processing in a first storage unit, a second processing unit for performing write processing in a second storage unit, a revealing data control unit for managing revealing data representing storage areas where the first processing unit has performed write processing in the first storage unit (101), another revealing data control unit for managing another revealing data representing storage areas where the second processing unit has performed write processing in the second storage unit, a priority data control unit for managing priority data representing a priority of each of the first and second processing units in units of storage areas of the second storage unit, a inhibition data control unit for managing inhibition data for inhibiting write processing in each storage area of the second storage unit using the priority data and the revealing data, and a processing data reflection unit for writing the da

Abstract: A storage means control apparatus of this invention includes a first processing unit for performing write processing in a first storage unit, a second processing unit for performing write processing in a second storage unit, a revealing data control unit for managing revealing data representing storage areas where the first processing unit has performed write processing in the first storage unit (101), another revealing data control unit for managing another revealing data representing storage areas where the second processing unit has performed write processing in the second storage unit, a priority data control unit for managing priority data representing a priority of each of the first and second processing units in units of storage areas of the second storage unit, a inhibition data control unit for managing inhibition data for inhibiting write processing in each storage area of the second storage unit using the priority data and the revealing data, and a processing data reflection unit for writing the da

Abstract: An input cell processing portion 11 and an output cell processing portion 12 in a line interface 10 execute a normal ATM process and an insertion/divergence process etc with respect to an input cell flow and an output cell flow. A cell buffer 40 is constructed on an external memory device to accumulate a template (format) of ATM cells to be processed. The input cell processing portion 11 or the output cell processing unit 12 in the line interface 10 judges whether a necessity for inserting the network management cell might arise or not when processing the input cell flow. Upon detecting herein that the insertion necessity arises, the management cell template previously held on the cell buffer 40 is read, and, after a necessary data replacing process has been executed thereon, the management cell is inserted into the input cell flow or the output cell flow.