Patents by Inventor Toshio Kumamoto
Toshio Kumamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9473088Abstract: A signal processing circuit includes a chopper amplifier that has a differential amplifier circuit that amplifies differential input signals Vsp(t) and Vsm(t), and an adder circuit that generates an addition signal Vfil(t) by addition of the chopper output signal Vsub(t) that the chopper amplifier generates. Differential signals inputted into the differential amplifier circuit are interchanged for every first phase period and second phase period, and the adder circuit generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period.Type: GrantFiled: August 17, 2015Date of Patent: October 18, 2016Assignee: Renesas Electronics CorporationInventors: Yoshihiro Funato, Toshio Kumamoto, Tomoaki Yoshizawa, Kazuaki Kurooka
-
Publication number: 20150357980Abstract: A signal processing circuit includes a chopper amplifier that has a differential amplifier circuit that amplifies differential input signals Vsp(t) and Vsm(t), and an adder circuit that generates an addition signal Vfil(t) by addition of the chopper output signal Vsub(t) that the chopper amplifier generates. Differential signals inputted into the differential amplifier circuit are interchanged for every first phase period and second phase period, and the adder circuit generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period.Type: ApplicationFiled: August 17, 2015Publication date: December 10, 2015Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yoshihiro FUNATO, Toshio KUMAMOTO, Tomoaki YOSHIZAWA, Kazuaki KUROOKA
-
Patent number: 9166541Abstract: A signal processing circuit includes a chopper amplifier that has a differential amplifier circuit that amplifies differential input signals Vsp(t) and Vsm(t), and an adder circuit that generates an addition signal Vfil(t) by addition of the chopper output signal Vsub(t) that the chopper amplifier generates. Differential signals inputted into the differential amplifier circuit are interchanged for every first phase period and second phase period, and the adder circuit generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period.Type: GrantFiled: April 16, 2014Date of Patent: October 20, 2015Assignee: Renesas Electronics CorporationInventors: Yoshihiro Funato, Toshio Kumamoto, Tomoaki Yoshizawa, Kazuaki Kurooka
-
Patent number: 9118341Abstract: A delta-sigma A/D converter having plural input channels comprises a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer.Type: GrantFiled: June 14, 2012Date of Patent: August 25, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Matsumoto, Toshio Kumamoto, Takashi Okuda
-
Publication number: 20140340145Abstract: A signal processing circuit includes a chopper amplifier that has a differential amplifier circuit that amplifies differential input signals Vsp(t) and Vsm(t), and an adder circuit that generates an addition signal Vfil(t) by addition of the chopper output signal Vsub(t) that the chopper amplifier generates. Differential signals inputted into the differential amplifier circuit are interchanged for every first phase period and second phase period, and the adder circuit generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period.Type: ApplicationFiled: April 16, 2014Publication date: November 20, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yoshihiro FUNATO, Toshio KUMAMOTO, Tomoaki YOSHIZAWA, Kazuaki KUROOKA
-
Publication number: 20130057419Abstract: A delta-sigma A/D converter having plural input channels comprises a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer.Type: ApplicationFiled: June 14, 2012Publication date: March 7, 2013Applicant: Renesas Electronics CorporationInventors: Takashi MATSUMOTO, Toshio KUMAMOTO, Takashi OKUDA
-
Patent number: 8330199Abstract: To eliminate the substrate voltage dependences of the respective resistance values of resistor elements, in the resistor elements coupled in series to each other over respective substrate regions, the ends of the resistor elements are coupled to the corresponding substrate regions by respective bias wires such that respective average potentials between the substrate regions of the resistor elements and the corresponding resistor elements have opposite polarities, and equal magnitudes.Type: GrantFiled: September 30, 2009Date of Patent: December 11, 2012Assignee: Renesas Electronics CorporationInventors: Masaomi Kamakura, Toshio Kumamoto, Takashi Okuda
-
Patent number: 8237282Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.Type: GrantFiled: February 18, 2011Date of Patent: August 7, 2012Assignees: Renesas Electronics Corporation, Renesas Device Design Corp.Inventors: Takashi Okuda, Yasuo Morimoto, Yuko Maruyama, Toshio Kumamoto
-
Patent number: 8223050Abstract: In a delta-sigma A/D converter provided with plural channels for converting an analog input signal into a digital signal, an adverse influence of an idle tone is reduced in each channel. The delta-sigma A/D converter comprises: a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer.Type: GrantFiled: October 25, 2010Date of Patent: July 17, 2012Assignee: Renesas Electronics CorporationInventors: Takashi Matsumoto, Toshio Kumamoto, Takashi Okuda
-
Patent number: 8188526Abstract: It is an object of the present invention to surely protect a predetermined semiconductor element or a predetermined semiconductor element group in an analog block from a noise generated from a digital block. A semiconductor device according to the present invention includes a semiconductor substrate, a digital block to be a region in which a digital circuit is formed and an analog block to be a region in which an analog circuit is formed, arranged by separating an upper surface of the semiconductor substrate and a substrate potential fixing region provided on the semiconductor substrate so as to surround in a planar view the predetermined semiconductor element group in the analog block, and a pad connected to the substrate potential fixing region and receiving a predetermined potential from an external part.Type: GrantFiled: December 2, 2010Date of Patent: May 29, 2012Assignee: Renesas Electronics CorporationInventors: Takashi Okuda, Toshio Kumamoto
-
Patent number: 8089136Abstract: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.Type: GrantFiled: September 27, 2010Date of Patent: January 3, 2012Assignee: Renesas Electronics CorporationInventors: Hiroyuki Amishiro, Toshio Kumamoto, Motoshige Igarashi, Kenji Yamaguchi
-
Publication number: 20110140277Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.Type: ApplicationFiled: February 18, 2011Publication date: June 16, 2011Applicants: Renesas Electronics Corporation, Renesas Device Design Corp.Inventors: Takashi OKUDA, Yasuo Morimoto, Yuko Maruyama, Toshio Kumamoto
-
Patent number: 7952506Abstract: There is provided a technique for reducing the adverse effect of idle tones in the channels in a ??-type A/D converter including a plurality of channels for converting analog input signals into digital signals. The ??-type A/D converter includes an L channel for converting a left analog input signal into a digital signal and an R channel for converting a right analog input signal into a digital signal. Each of the L channel and the R channel includes a DC dither circuit for generating a DC addition voltage for shifting the frequency of an idle tone. In the L channel and the R channel, DC addition voltages generated by DC dither circuits are different from each other.Type: GrantFiled: October 25, 2010Date of Patent: May 31, 2011Assignee: Renesas Electronics CorporationInventors: Toshio Kumamoto, Takashi Okuda, Tatsuo Sengoku, Akira Kitaguchi
-
Publication number: 20110095925Abstract: In a delta-sigma A/D converter provided with plural channels for converting an analog input signal into a digital signal, an adverse influence of an idle tone is reduced in each channel. The delta-sigma A/D converter comprises: a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer.Type: ApplicationFiled: October 25, 2010Publication date: April 28, 2011Inventors: Takashi MATSUMOTO, Toshio Kumamoto, Takashi Okuda
-
Patent number: 7915708Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.Type: GrantFiled: June 16, 2009Date of Patent: March 29, 2011Assignees: Renesas Electronics Corporation, Renesas Device Design Corp.Inventors: Takashi Okuda, Yasuo Morimoto, Yuko Maruyama, Toshio Kumamoto
-
Publication number: 20110068383Abstract: It is an object of the present invention to surely protect a predetermined semiconductor element or a predetermined semiconductor element group in an analog block from a noise generated from a digital block. A semiconductor device according to the present invention includes a semiconductor substrate, a digital block to be a region in which a digital circuit is formed and an analog block to be a region in which an analog circuit is formed, arranged by separating an upper surface of the semiconductor substrate and a substrate potential fixing region provided on the semiconductor substrate so as to surround in a planar view the predetermined semiconductor element group in the analog block, and a pad connected to the substrate potential fixing region and receiving a predetermined potential from an external part.Type: ApplicationFiled: December 2, 2010Publication date: March 24, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Okuda, Toshio Kumamoto
-
Publication number: 20110037633Abstract: There is provided a technique for reducing the adverse effect of idle tones in the channels in a ??-type A/D converter including a plurality of channels for converting analog input signals into digital signals. The ??-type A/D converter includes an L channel for converting a left analog input signal into a digital signal and an R channel for converting a right analog input signal into a digital signal. Each of the L channel and the R channel includes a DC dither circuit for generating a DC addition voltage for shifting the frequency of an idle tone. In the L channel and the R channel, DC addition voltages generated by DC dither circuits are different from each other.Type: ApplicationFiled: October 25, 2010Publication date: February 17, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Toshio KUMAMOTO, Takashi Okuda, Tatsuo Sengoku, Akira Kitaguchi
-
Publication number: 20110012231Abstract: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.Type: ApplicationFiled: September 27, 2010Publication date: January 20, 2011Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Hiroyuki AMISHIRO, Toshio Kumamoto, Motoshige Igarashi, Kenji Yamaguchi
-
Patent number: 7868413Abstract: It is an object of the present invention to surely protect a predetermined semiconductor element or a predetermined semiconductor element group in an analog block from a noise generated from a digital block. A semiconductor device according to the present invention includes a semiconductor substrate, a digital block to be a region in which a digital circuit is formed and an analog block to be a region in which an analog circuit is formed, arranged by separating an upper surface of the semiconductor substrate and a substrate potential fixing region provided on the semiconductor substrate so as to surround in a planar view the predetermined semiconductor element group in the analog block, and a pad connected to the substrate potential fixing region and receiving a predetermined potential from an external part.Type: GrantFiled: November 7, 2008Date of Patent: January 11, 2011Assignee: Renesas Electronics CorporationInventors: Takashi Okuda, Toshio Kumamoto
-
Patent number: 7847714Abstract: There is provided a technique for reducing the adverse effect of idle tones in the channels in a ??-type A/D converter including a plurality of channels for converting analog input signals into digital signals. The ??-type A/D converter includes an L channel for converting a left analog input signal into a digital signal and an R channel for converting a right analog input signal into a digital signal. Each of the L channel and the R channel includes a DC dither circuit for generating a DC addition voltage for shifting the frequency of an idle tone. In the L channel and the R channel, DC addition voltages generated by DC dither circuits are different from each other.Type: GrantFiled: March 25, 2009Date of Patent: December 7, 2010Assignee: Renesas Electronics CorporationInventors: Toshio Kumamoto, Takashi Okuda, Tatsuo Sengoku, Akira Kitaguchi