Patents by Inventor Toshio Kumamoto
Toshio Kumamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7821078Abstract: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.Type: GrantFiled: January 11, 2008Date of Patent: October 26, 2010Assignee: Renesas Electronics CorporationInventors: Hiroyuki Amishiro, Toshio Kumamoto, Motoshige Igarashi, Kenji Yamaguchi
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Publication number: 20100109775Abstract: To eliminate the substrate voltage dependences of the respective resistance values of resistor elements, in the resistor elements coupled in series to each other over respective substrate regions, the ends of the resistor elements are coupled to the corresponding substrate regions by respective bias wires such that respective average potentials between the substrate regions of the resistor elements and the corresponding resistor elements have opposite polarities, and equal magnitudes.Type: ApplicationFiled: September 30, 2009Publication date: May 6, 2010Inventors: Masaomi KAMAKURA, Toshio Kumamoto, Takashi Okuda
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Patent number: 7710304Abstract: In an A/D converter including a switched capacitor integration circuit, to suppress an effect of a noise generated in the switched capacitor circuit while suppressing increase in a forming area of the circuit. A first-stage integrator of a differential input type A/D converter includes first and second switched capacitor circuits, and includes a noise cancel circuit for generating a noise cancel signal to cancel a kickback noise generated due to switching operation thereof.Type: GrantFiled: July 23, 2008Date of Patent: May 4, 2010Assignee: Renesas Technology Corp.Inventors: Toshio Kumamoto, Takashi Okuda
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Publication number: 20090267816Abstract: There is provided a technique for reducing the adverse effect of idle tones in the channels in a ??-type A/D converter including a plurality of channels for converting analog input signals into digital signals. The ??-type A/D converter includes an L channel for converting a left analog input signal into a digital signal and an R channel for converting a right analog input signal into a digital signal. Each of the L channel and the R channel includes a DC dither circuit for generating a DC addition voltage for shifting the frequency of an idle tone. In the L channel and the R channel, DC addition voltages generated by DC dither circuits are different from each other.Type: ApplicationFiled: March 25, 2009Publication date: October 29, 2009Inventors: Toshio KUMAMOTO, Takashi OKUDA, Tatsuo SENGOKU, Akira KITAGUCHI
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Publication number: 20090250788Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction, a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.Type: ApplicationFiled: June 16, 2009Publication date: October 8, 2009Applicants: Renesas Technology Corp., Renesas Device Design Corp.Inventors: Takashi OKUDA, Yasuo Morimoto, Yuko Maruyama, Toshio Kumamoto
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Patent number: 7557427Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.Type: GrantFiled: August 27, 2007Date of Patent: July 7, 2009Assignees: Renesas Technology Corp., Renesas Device Design Corp.Inventors: Takashi Okuda, Yasuo Morimoto, Yuko Maruyama, Toshio Kumamoto
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Publication number: 20090127713Abstract: It is an object of the present invention to surely protect a predetermined semiconductor element or a predetermined semiconductor element group in an analog block from a noise generated from a digital block. A semiconductor device according to the present invention includes a semiconductor substrate, a digital block to be a region in which a digital circuit is formed and an analog block to be a region in which an analog circuit is formed, arranged by separating an upper surface of the semiconductor substrate and a substrate potential fixing region provided on the semiconductor substrate so as to surround in a planar view the predetermined semiconductor element group in the analog block, and a pad connected to the substrate potential fixing region and receiving a predetermined potential from an external part.Type: ApplicationFiled: November 7, 2008Publication date: May 21, 2009Inventors: Takashi OKUDA, Toshio KUMAMOTO
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Publication number: 20090027247Abstract: In an A/D converter including a switched capacitor integration circuit, to suppress an effect of a noise generated in the switched capacitor circuit while suppressing increase in a forming area of the circuit. A first-stage integrator of a differential input type A/D converter includes first and second switched capacitor circuits, and includes a noise cancel circuit for generating a noise cancel signal to cancel a kickback noise generated due to switching operation thereof.Type: ApplicationFiled: July 23, 2008Publication date: January 29, 2009Inventors: Toshio KUMAMOTO, Takashi Okuda
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Patent number: 7446390Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.Type: GrantFiled: August 27, 2007Date of Patent: November 4, 2008Assignees: Renesas Technology Corp., Renesas Device Design Corp.Inventors: Takashi Okuda, Yasuo Morimoto, Yuko Maruyama, Toshio Kumamoto
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Publication number: 20080116526Abstract: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.Type: ApplicationFiled: January 11, 2008Publication date: May 22, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hiroyuki Amishiro, Toshio Kumamoto, Motoshige Igarashi, Kenji Yamaguchi
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Patent number: 7362194Abstract: An oscillator circuit is formed of a differential LC resonant circuit formed of an L load differential circuit including inductance-variable portions and a capacitor element, and a positive feedback circuit formed of N-channel MOS transistors. The inductance-variable portion is configured to vary the inductance by selecting a plurality of switch circuits arranged between a plurality of arbitrary positions on a spiral interconnection layer and the input/output terminal, and thereby can control an oscillation frequency. The inductance-variable portions form an inductor pair when the switch circuit among the switch circuits coupled between the first input/output terminals is turned on together with the switch circuit.Type: GrantFiled: February 20, 2007Date of Patent: April 22, 2008Assignee: Renesas Technology Corp.Inventors: Hiroshi Komurasaki, Tomohiro Sano, Hisayasu Sato, Toshio Kumamoto, Yasushi Hashizume
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Publication number: 20080001255Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.Type: ApplicationFiled: August 27, 2007Publication date: January 3, 2008Applicants: Renesas Technology Corp., Renesas Device Design Corp.Inventors: Takashi OKUDA, Yasuo Morimoto, Yuko Maruyama, Toshio Kumamoto
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Publication number: 20070296059Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.Type: ApplicationFiled: August 27, 2007Publication date: December 27, 2007Applicants: Renesas Technology Corp., Renesas Device Design Corp.Inventors: Takashi OKUDA, Yasuo Morimoto, Yuko Maruyama, Toshio Kumamoto
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Patent number: 7276776Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.Type: GrantFiled: December 17, 2004Date of Patent: October 2, 2007Assignees: Renesas Technology Corp., Renesas Device Design Corp.Inventors: Takashi Okuda, Yasuo Morimoto, Yuko Maruyama, Toshio Kumamoto
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Publication number: 20070146089Abstract: An oscillator circuit is formed of a differential LC resonant circuit formed of an L load differential circuit including inductance-variable portions and a capacitor element, and a positive feedback circuit formed of N-channel MOS transistors. The inductance-variable portion is configured to vary the inductance by selecting a plurality of switch circuits arranged between a plurality of arbitrary positions on a spiral interconnection layer and the input/output terminal, and thereby can control an oscillation frequency. The inductance-variable portions form an inductor pair when the switch circuit among the switch circuits coupled between the first input/output terminals is turned on together with the switch circuit.Type: ApplicationFiled: February 20, 2007Publication date: June 28, 2007Inventors: Hiroshi Komurasaki, Tomohiro Sano, Hisayasu Sato, Toshio Kumamoto, Yasushi Hashizume
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Patent number: 7202754Abstract: An oscillator circuit is formed of a differential LC resonant circuit formed of an L load differential circuit including inductance-variable portions and a capacitive element, and a positive feedback circuit formed of N-channel MOS transistors. The inductance-variable portion is configured to vary the inductance by selecting a plurality of switch circuits arranged between a plurality of arbitrary positions on a spiral interconnection layer and the input/output terminal, and thereby can control an oscillation frequency. The inductance-variable portions form an inductor pair when the switch circuit among the switch circuits coupled between the first input/output terminals is turned on together with the switch circuit.Type: GrantFiled: November 17, 2005Date of Patent: April 10, 2007Assignee: Renesas Technology Corp.Inventors: Hiroshi Komurasaki, Tomohiro Sano, Hisayasu Sato, Toshio Kumamoto, Yasushi Hashizume
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Publication number: 20060175679Abstract: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.Type: ApplicationFiled: March 21, 2006Publication date: August 10, 2006Applicant: Renesas Technology Corp.Inventors: Hiroyuki Amishiro, Toshio Kumamoto, Motoshige Igarashi, Kenji Yamaguchi
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Patent number: 7045865Abstract: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.Type: GrantFiled: September 24, 2001Date of Patent: May 16, 2006Assignee: Renesas Technology Corp.Inventors: Hiroyuki Amishiro, Toshio Kumamoto, Motoshige Igarashi, Kenji Yamaguchi
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Publication number: 20060071732Abstract: An oscillator circuit is formed of a differential LC resonant circuit formed of an L load differential circuit including inductance-variable portions and a capacitive element, and a positive feedback circuit formed of N-channel MOS transistors. The inductance-variable portion is configured to vary the inductance by selecting a plurality of switch circuits arranged between a plurality of arbitrary positions on a spiral interconnection layer and the input/output terminal, and thereby can control an oscillation frequency. The inductance-variable portions form an inductor pair when the switch circuit among the switch circuits coupled between the first input/output terminals is turned on together with the switch circuit.Type: ApplicationFiled: November 17, 2005Publication date: April 6, 2006Applicant: RENESAS TECHNOLOGY CORPORATIONInventors: Hiroshi Komurasaki, Tomohiro Sano, Hisayasu Sato, Toshio Kumamoto, Yasushi Hashizume
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Patent number: 7009539Abstract: A ?? modulator modulates only an error component separated by a component separating portion. Therefore, even if the number of order of the ?? modulator increases, an amplitude of an output of an integrator in the final stage does not excessively increase, and the stability of the modulator can be achieved. Since the signal component separated by the component separating portion does not pass through the ?? modulator, an intensity of an input signal can be maintained as it is, and the modulator can have high precision.Type: GrantFiled: November 19, 2003Date of Patent: March 7, 2006Assignee: Renesas Technology Corp.Inventors: Takashi Okuda, Toshio Kumamoto, Yasuo Morimoto