Abstract: A signal processing device includes: an amplifier, a bandwidth of which can be switched, and a controller which is configured to perform control to operate the amplifier in a wide bandwidth for a constant time after start of a signal input to the amplifier and then operate the amplifier in a narrow bandwidth thereafter.

Abstract: An offset cancel circuit includes a first amplifying section, a second amplifying section, a third resistor connected between a non-inverting input terminal of the first amplifying section and a non-inverting input terminal of the second amplifying section, and a current source. In the offset cancel circuit, the current source causes a constant current to flow through the third resistor to cancel an offset voltage from output signals of first and second amplifying sections, the constant current corresponding to the offset voltage contained in first and second output signals output from a bridge resistance type sensor.

Abstract: A signal processing device includes: an amplifier, a bandwidth of which can be switched, and a controller which is configured to perform control to operate the amplifier in a wide bandwidth for a constant time after start of a signal input to the amplifier and then operate the amplifier in a narrow bandwidth thereafter.

Abstract: An offset cancel circuit includes a first amplifying section, a second amplifying section, a third resistor connected between a non-inverting input terminal of the first amplifying section and a non-inverting input terminal of the second amplifying section, and a current source. In the offset cancel circuit, the current source causes a constant current to flow through the third resistor to cancel an offset voltage from output signals of first and second amplifying sections, the constant current corresponding to the offset voltage contained in first and second output signals output from a bridge resistance type sensor.

Abstract: A voltage generation circuit includes a voltage detection circuit that generates a detection voltage according to an output voltage, a reference voltage generation circuit that generates a reference voltage which changes periodically, a comparison circuit that generates a control signal according to a result of a comparison between the detection voltage and the reference voltage, wherein control pulses each having a pulse width according to the detection voltage are sequentially appeared in the control signal, and a driving pulse generation circuit that generates a driving pulse corresponding to the control pulse and supplies the generated driving pulse to a transistor connected to a DC power source when the pulse width of the control pulse exceeds a predetermined width, and stops generating the driving pulse when the pulse width of the control pulse becomes smaller than the predetermined width.

Abstract: A class D amplifier includes an amplifier that generates a digital signal for driving a load based on an input signal, an attenuator that attenuates the input signal according to an attenuation command signal, and a clip prevention controller that outputs the attenuation command signal to intermittently attenuate the input signal when the digital signal is brought into a clip state or a near-clip state.

Abstract: A class-D amplifier for generating from an input signal a digital signal for driving a load, includes an output limit instruction generating section that detects that the digital signal falls outside a limit range and that outputs an output limit instruction signal, an attenuation instruction pulse generating section that includes an integrator for integrating the output limit instruction signal and that outputs a periodical attenuation instruction pulse having pulse width corresponding to an integrated value in the integrator, an attenuating section provided in an input path for the input signal and that attenuates the input signal based on the attenuation instruction pulse, and a mute control section that controls the integrated value in the integrator independently of the output limit instruction signal to control an amount of the attenuation of the attenuating section applied to the input signal.

Abstract: A voltage adder circuit includes an amplifier circuit having a first operational amplifier and into which a first voltage is input, a circuit that supplies an output current to the amplifier circuit, and a current providing section that detects the output current of the circuit and supplies an output current equal to the output current of the circuit in magnitude so that the output current of the circuit is prevented from inputting to or outputting from the first operational amplifier through an output terminal of the first operational amplifier. A second voltage is input into the circuit.

Abstract: A voltage generation circuit includes a voltage detection circuit that generates a detection voltage according to an output voltage, a reference voltage generation circuit that generates a reference voltage which changes periodically, a comparison circuit that generates a control signal according to a result of a comparison between the detection voltage and the reference voltage, wherein control pulses each having a pulse width according to the detection voltage are sequentially appeared in the control signal, and a driving pulse generation circuit that generates a driving pulse corresponding to the control pulse and supplies the generated driving pulse to a transistor connected to a DC power source when the pulse width of the control pulse exceeds a predetermined width, and stops generating the driving pulse when the pulse width of the control pulse becomes smaller than the predetermined width.

Abstract: A voltage generation circuit includes a voltage detection circuit that generates a detection voltage according to an output voltage, a reference voltage generation circuit that generates a reference voltage which changes periodically, a comparison circuit that generates a control signal according to a result of a comparison between the detection voltage and the reference voltage, wherein control pulses each having a pulse width according to the detection voltage are sequentially appeared in the control signal, and a driving pulse generation circuit that generates a driving pulse corresponding to the control pulse and supplies the generated driving pulse to a transistor connected to a DC power source when the pulse width of the control pulse exceeds a predetermined width, and stops generating the driving pulse when the pulse width of the control pulse becomes smaller than the predetermined width.

Abstract: A class D amplifier includes: an amplifier that generates a digital signal for driving a load based on an input signal; an attenuator that attenuates the input signal according to an attenuation command signal; and a clip prevention controller that outputs the attenuation command signal to intermittently attenuate the input signal when the digital signal is brought into a clip state or a near-clip state.

Abstract: A class D amplifier includes an amplifier that generates a digital signal for driving a load based on an input signal, an attenuator that attenuates the input signal according to an attenuation command signal, and a clip prevention controller that outputs the attenuation command signal to intermittently attenuate the input signal when the digital signal is brought into a clip state or a near-clip state.

Abstract: A voltage adder circuit includes an amplifier circuit having a first operational amplifier and into which a first voltage is input, a circuit that supplies an output current to the amplifier circuit, and a current providing section that detects the output current of the circuit and supplies an output current equal to the output current of the circuit in magnitude so that the output current of the circuit is prevented from inputting to or outputting from the first operational amplifier through an output terminal of the first operational amplifier. A second voltage is input into the circuit.

Abstract: A class-D amplifier for generating from an input signal a digital signal for driving a load, includes an output limit instruction generating section that detects that the digital signal falls outside a limit range and that outputs an output limit instruction signal, an attenuation instruction pulse generating section that includes an integrator for integrating the output limit instruction signal and that outputs a periodical attenuation instruction pulse having pulse width corresponding to an integrated value in the integrator, an attenuating section provided in an input path for the input signal and that attenuates the input signal based on the attenuation instruction pulse, and a mute control section that controls the integrated value in the integrator independently of the output limit instruction signal to control an amount of the attenuation of the attenuating section applied to the input signal.

Abstract: A PWM modulator adds first and second input signals to each other, and performs PWM modulation processing for outputting a PWM-modulated pulse whose pulse width is modulated according to a result of addition. A shift register delays a bit stream acquired from a ?? modulator, thereby generating two bit streams having a time difference which is one-half a period of PWM modulation processing, and the bit streams are supplied at first and second input signals to the PWM modulator.

Abstract: A DC/DC converter is constituted of a switching element (e.g., a MOS transistor), an LC low-pass filter constituted of an inductor and a capacitor, and a control circuit for controlling the on/off timing of the switching element such that the output voltage is set to a predetermined voltage value. A series circuit (serving as a snubber circuit) constituted of a resistor and a switch is further connected in parallel with the inductor. The control circuit closes the switch so that the resistor is connected in parallel with the inductor in a resonance mode of the LC low-pass filter. Thus, it is possible to dissipate energy accumulated in the inductor in a short time without using a relatively large circuit scale, thus avoiding the occurrence of ringing.

Abstract: A class D amplifier includes: an amplifier that generates a digital signal for driving a load based on an input signal; an attenuator that attenuates the input signal according to an attenuation command signal; and a clip prevention controller that outputs the attenuation command signal to intermittently attenuate the input signal when the digital signal is brought into a clip state or a near-clip state.

Abstract: A class D amplifier includes: an amplifier that generates a digital signal for driving a load based on an input signal; an attenuator that attenuates the input signal according to an attenuation command signal; and a clip prevention controller that outputs the attenuation command signal to intermittently attenuate the input signal when the digital signal is brought into a clip state or a near-clip state.

Abstract: PWM signals having different polarities input from a +IN terminal and a ?IN terminal are output to a pre-driver and a switching signal generation circuit. The pre-driver outputs to switches a gate signal for actuating a driver obtained from the input PWM signal. The switching signal generation circuit inputs a PWM signal and outputs switching signals. A switching circuit, on input of the switching signals, changes over switches so that the gate signal is output to a first P-channel MOS transistor and a first N-channel MOS transistor in case the PWM signal is input from the +IN side, and to a second P-channel MOS transistor and a second N-channel MOS transistor in case the PWM signal is input from the ?IN side.

Abstract: A PWM modulator adds first and second input signals to each other, and performs PWM modulation processing for outputting a PWM-modulated pulse whose pulse width is modulated according to a result of addition. A shift register delays a bit stream acquired from a ?? modulator, thereby generating two bit streams having a time difference which is one-half a period of PWM modulation processing, and the bit streams are supplied at first and second input signals to the PWM modulator.