Abstract: PWM signals having different polarities input from a +IN terminal and a ?IN terminal are output to a pre-driver and a switching signal generation circuit. The pre-driver outputs to switches a gate signal for actuating a driver obtained from the input PWM signal. The switching signal generation circuit inputs a PWM signal and outputs switching signals. A switching circuit, on input of the switching signals, changes over switches so that the gate signal is output to a first P-channel MOS transistor and a first N-channel MOS transistor in case the PWM signal is input from the +IN side, and to a second P-channel MOS transistor and a second N-channel MOS transistor in case the PWM signal is input from the ?IN side.

Abstract: A class D amplifier includes: an amplifier that generates a digital signal for driving a load based on an input signal; an attenuator that attenuates the input signal according to an attenuation command signal; and a clip prevention controller that outputs the attenuation command signal to intermittently attenuate the input signal when the digital signal is brought into a clip state or a near-clip state.

Abstract: An amplitude adjustment device such as an amplitude compression device and amplitude expansion device is basically configured by a PWM modulator, a demodulator and an amplitude detector. Herein, the PWM modulator effects pulse-width modulation on an input signal to produce a pulse-width modulated signal, which is demodulated by the demodulator to produce an output signal. In addition, the amplitude detector detects an amplitude of a demodulated signal or an amplitude of the input signal to produce a control signal. A modulation factor of the pulse-width modulation is adjusted based on the control signal. In the case of the amplitude compression device, an input/output gain is changed inversely proportional to the amplitude of the input signal or amplitude of the output signal. Thus, it is possible to compress a dynamic range with respect to input/output characteristics.

Abstract: A class-D amplifier for pulse-width-modulating an analog input signal to output a pulse-width-modulated signal, includes: a differentiating circuit for differentiating the pulse-width-modulated signal of the class-D amplifier; and a negative feedback circuit for feeding back the differentiated signal of the differentiating circuit to an input side of the class-D amplifier in a negative feedback manner.

Abstract: A class-D amplifier includes: an operational amplifier and capacitors, which constitute an integrator for integrating a difference between a plus-sided input signal and a minus-sided input signal which constitute analog input signals; delay circuits for delaying a phase of a triangular wave by a desirable very small angle; resistors, which constitute a synthesizing circuit for synthesizing an output of the integrator, the triangular wave, and outputs of the delay circuits with each other; comparators for comparing outputs of the synthesizing circuit with each other; AND circuits which constitute a buffer for inputting outputs of the comparators; and resistors feeding back an output of the buffer to an input side of the integrator.

Abstract: A pulse width modulation (PWM) amplifier which is capable of reducing unwanted radiation from a PWM output thereof, which can cause EMI, while reducing manufacturing costs thereof. A triangular wave-generating circuit (3) of the PWM amplifier outputs a triangular wave. The triangular wave has a waveform steep or gentle in pulse rising and falling slopes dependent on a value of current flowing through an FET (116) or an FET (117). The value of current is changed by a current flowing through a FET (112). A switching element (32) changes voltage applied to the gate of an FET (110), for control of increase and decrease in the current flowing through the FET (112). This enables the triangular wave to be generated such that it is formed by pulses having different periods. An input signal is subjected to PWM amplification based on the triangular wave generated.

Abstract: An amplitude adjustment device such as an amplitude compression device and amplitude expansion device is basically configured by a PWM modulator, a demodulator and an amplitude detector. Herein, the PWM modulator effects pulse-width modulation on an input signal to produce a pulse-width modulated signal, which is demodulated by the demodulator to produce an output signal. In addition, the amplitude detector detects an amplitude of a demodulated signal or an amplitude of the input signal to produce a control signal. A modulation factor of the pulse-width modulation is adjusted based on the control signal. In the case of the amplitude compression device, an input/output gain is changed inversely proportional to the amplitude of the input signal or amplitude of the output signal. Thus, it is possible to compress a dynamic range with respect to input/output characteristics.

Abstract: A class-D amplifier for pulse-width-modulating an analog input signal to output a pulse-width-modulated signal, includes: a differentiating circuit for differentiating the pulse-width-modulated signal of the class-D amplifier; and a negative feedback circuit for feeding back the differentiated signal of the differentiating circuit to an input side of the class-D amplifier in a negative feedback manner.

Abstract: A class-D amplifier includes: an operational amplifier and capacitors, which constitute an integrator for integrating a difference between a plus-sided input signal and a minus-sided input signal which constitute analog input signals; delay circuits for delaying a phase of a triangular wave by a desirable very small angle; resistors, which constitute a synthesizing circuit for synthesizing an output of the integrator, the triangular wave, and outputs of the delay circuits with each other; comparators for comparing outputs of the synthesizing circuit with each other; AND circuits which constitute a buffer for inputting outputs of the comparators; and resistors feeding back an output of the buffer to an input side of the integrator.

Abstract: A signal level shift circuit is provided for different circuit systems operating based on different supply voltages (VDDL, VDDH), wherein a supply voltage detection circuit detects a reduction of a first supply voltage (VDDL) regarding an input signal (IN). A level shift circuit comprises a load circuit portion consisting of PMOS transistors and a drive circuit portion consisting of NMOS transistors, all of which are connected together to form current paths. A switch circuit arranged for the current paths opens when a reduction is detected in the first supply voltage so that both the NMOS transistors are turned on. Thus, it is possible to effectively avoid occurrence of through currents flowing in the level shift circuit. The level shift circuit is followed by a flip-flop, which provides an output signal (OUT) in conformity with a second supply voltage (VDDH).

Abstract: An amplitude adjustment device such as an amplitude compression device and amplitude expansion device is basically configured by a PWM modulator, a demodulator and an amplitude detector. Herein, the PWM modulator effects pulse-width modulation on an input signal to produce a pulse-width modulated signal, which is demodulated by the demodulator to produce an output signal. In addition, the amplitude detector detects an amplitude of a demodulated signal or an amplitude of the input signal to produce a control signal. A modulation factor of the pulse-width modulation is adjusted based on the control signal. In the case of the amplitude compression device, an input/output gain is changed inversely proportional to the amplitude of the input signal or amplitude of the output signal. Thus, it is possible to compress a dynamic range with respect to input/output characteristics.

Abstract: A pulse width modulation (PWM) amplifier which is capable of reducing unwanted radiation from a PWM output thereof, which can cause EMI, while reducing manufacturing costs thereof. A triangular wave-generating circuit (3) of the PWM amplifier outputs a triangular wave. The triangular wave has a waveform steep or gentle in pulse rising and falling slopes dependent on a value of current flowing through an FET (116) or an FET (117). The value of current is changed by a current flowing through a FET (112). A switching element (32) changes voltage applied to the gate of an FET (110), for control of increase and decrease in the current flowing through the FET (112). This enables the triangular wave to be generated such that it is formed by pulses having different periods. An input signal is subjected to PWM amplification based on the triangular wave generated.

Abstract: An amplitude adjustment device such as an amplitude compression device and amplitude expansion device is basically configured by a PWM modulator, a demodulator and an amplitude detector. Herein, the PWM modulator effects pulse-width modulation on an input signal to produce a pulse-width modulated signal, which is demodulated by the demodulator to produce an output signal. In addition, the amplitude detector detects an amplitude of a demodulated signal or an amplitude of the input signal to produce a control signal. A modulation factor of the pulse-width modulation is adjusted based on the control signal. In the case of the amplitude compression device, an input/output gain is changed inversely proportional to the amplitude of the input signal or amplitude of the output signal. Thus, it is possible to compress a dynamic range with respect to input/output characteristics.

Abstract: Level shift circuit includes an operational amplifier, and an input resistor having one end connected to an output terminal of an amplifier circuit and the other end connected to the inverted input terminal of the operational amplifier. The level shift circuit further includes a level-shifting resistor of a resistance value R0 having one end connected to the inverted input terminal of the operational amplifier and the other end connected to a ground, and a feedback resistor of a resistance value R1. Reference voltage Vref is applied to the noninverted input terminal of the operational amplifier. Output signal of the level shift circuit represents the output of the amplifier circuit having been shifted in level by a predetermined amount.

Abstract: A signal level shift circuit is provided for different circuit systems operating based on different supply voltages (VDDL, VDDH), wherein a supply voltage detection circuit detects a reduction of a first supply voltage (VDDL) regarding an input signal (IN). A level shift circuit comprises a load circuit portion consisting of PMOS transistors and a drive circuit portion consisting of NMOS transistors, all of which are connected together to form current paths. A switch circuit arranged for the current paths opens when a reduction is detected in the first supply voltage so that both the NMOS transistors are turned on. Thus, it is possible to effectively avoid occurrence of through currents flowing in the level shift circuit. The level shift circuit is followed by a flip-flop, which provides an output signal (OUT) in conformity with a second supply voltage (VDDH).

Abstract: A differential amplifier circuit of the present invention comprises an input circuit 10 for producing a difference voltage signal between a positive input signal and a negative input signal, a feedback bias circuit 20 for inputting the difference voltage signal supplied from the input circuit 10 to provide a bias voltage corresponding to the difference voltage signal and for performing a feedback control on the bias voltage by feeding back an output current, an output circuit 30 for supplying a load with the output current corresponding to the bias voltage, and a current detection circuit 40 for detecting the output current to provide it to the feedback bias circuit 20. The differential amplifier circuit performs class-AB amplification in such a way that the bias voltage provides a current value close to zero when the difference voltage signal is substantially zero.

Abstract: A differential amplifier circuit of the present invention comprises an input circuit 10 for producing a difference voltage signal between a positive input signal and a negative input signal, a feedback bias circuit 20 for inputting the difference voltage signal supplied from the input circuit 10 to provide a bias voltage corresponding to the difference voltage signal and for performing a feedback control on the bias voltage by feeding back an output current, an output circuit 30 for supplying a load with the output current corresponding to the bias voltage, and a current detection circuit 40 for detecting the output current to provide it to the feedback bias circuit 20. The differential amplifier circuit performs class-AB amplification in such a way that the bias voltage provides a current value close to zero when the difference voltage signal is substantially zero.

Abstract: Level shift circuit includes an operational amplifier, and an input resistor having one end connected to an output terminal of an amplifier circuit and the other end connected to the inverted input terminal of the operational amplifier. The level shift circuit further includes a level-shifting resistor of a resistance value RO having one end connected to the inverted input terminal of the operational amplifier and the other end connected to a ground, and a feedback resistor of a resistance value R1. Reference voltage Vref is applied to the noninverted input terminal of the operational amplifier. Output signal of the level shift circuit represents the output of the amplifier circuit having been shifted in level by a predetermined amount.

Abstract: A delay circuit is provided, which is capable of eliminating the influence of noise of low frequency as disturbance. A plurality of memory cells including a plurality of capacitors store an analog signal as an input signal by storing charge of the input signal in the capacitors. A first inverting device inverts the input signal to generate an inverted signal. A control circuit generates and delivers control signals to the memory cells to select the input signal and the inverted signal alternately and sequentially write the selected signals into the memory cells in a predetermined writing sequence. The control circuit further generates and delivers to the memory cells to sequentially read out the input signal and the inverted signal from the memory cells in a sequence corresponding to the predetermined writing sequence. A second inverting device inverts the read-out inverted signal. An output signal is synthesized from the read-out input signal and an output signal of the second inverting device.

Abstract: An analog-digital converter includes a .DELTA..SIGMA. modulator, a digital filter, a high-pass filter and a multiplier which are connected in series. Analog input is converted into serial-bit strings by the .DELTA..SIGMA. modulator, for which gain `1/A` is set. The digital filter extracts low-frequency components, corresponding to the analog input, from the serial-bit strings, so the low-frequency components are converted into parallel-bit digital data. The high-pass filter removes DC offset component from output of the digital filter; and then, output thereof is multiplied by scaling gain `A` by the multiplier so that digital output is produced. The .DELTA..SIGMA. modulator includes at least three switched-capacitor integrators and a one-bit quantizer, which are connected in series, as well as a one-sample delay circuit. One-bit output, produced by the one-bit quantizer, is delayed by the one-sample delay circuit, whose output is delivered to each switched-capacitor integrator.