Patents by Inventor Toshiomi Moriki

Toshiomi Moriki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210056530
    Abstract: An application executed at a user terminal with a touch screen displays, on the touch screen, a UI in which a user-side UI for accepting a touch operation by a user and a store-side UI for accepting a touch operation by a staff member of a store are placed, as a settlement UI for settlement of a currency amount of a digital local currency. The application judges whether time during which the touch operation on the user-side UI and the touch operation on the store-side UI are simultaneously continued has reached a specified period of time or not. If the judgment result is true, the application displays a settlement completion notice on the touch screen.
    Type: Application
    Filed: July 6, 2020
    Publication date: February 25, 2021
    Applicant: Hitachi, Ltd.
    Inventors: Toshiomi MORIKI, Yuuichi KUROSAWA, Hiroki SATOH, Miho KOBAYASHI
  • Publication number: 20210042828
    Abstract: An electronic community currency operation system S includes a user terminal 1, a store terminal 2 and a management server 3 connected via a network CN1. The management server 3 includes a premium amount determination unit F38 which receives, from the user terminal 1, an issue request of an electronic community currency received from a user, and determines an additional amount to be added to an issue amount of the electronic community currency, which is to be issued according to the received issue request, according to a current amount of circulation relative to an overall maximum issue of the electronic community currency, and a community currency issuing unit F35 which issues, according to the issue request, the electronic community currency in which the determined additional amount has been added to the issue amount, and notifies the issued electronic community currency to the user terminal 1.
    Type: Application
    Filed: May 28, 2020
    Publication date: February 11, 2021
    Inventors: Hiroki SATOH, Toshiomi MORIKI
  • Patent number: 10331474
    Abstract: A machine system includes a physical machine, a memory pool, and a memory pool management machine. The memory pool management machine manages, with respect to a memory region of the memory pool, an allocated region, a cleared region, and an uncleared region. When generating a virtual machine, a hypervisor in the physical machine sends a memory allocation request to the memory pool management machine. When a response, to the request, received from the memory pool management machine includes an address range belonging to the uncleared region, the hypervisor clears the memory region of the address range belonging to the uncleared region and then generates the virtual machine.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: June 25, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Imada, Toshiomi Moriki
  • Patent number: 10289564
    Abstract: A computer on which OSs run is coupled to the storage apparatus, the OSs include a first OS controlling access to the storage apparatus and a second OS generating a virtual computer. A logically divided computer resources are allocated to the first OS and the second OS respectively. A third OS for executing an application runs on the virtual computer. The second OS has a shared region management part managing a shared region that is a memory region used for communication between the application and the first OS. The third operating system has an agent requesting the second operating system to secure the shared region based on a request from the application and mapping the secured shared region to a guest virtual address space.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: May 14, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Yukari Hatta, Norimitsu Hayakawa, Takao Totsuka, Toshiomi Moriki, Satoshi Kinugawa
  • Patent number: 10210035
    Abstract: A computer system, having: a physical computer, which includes a processor and a memory; and an external apparatus, which is coupled to the physical computer and which includes a storage apparatus, the physical computer further includes: a virtualization module for providing at least one virtual machine; a first failure monitoring module for detecting a failure in the physical computer and the virtualization module; a first memory dump module for copying, to the external apparatus, a first area in the memory which is allocated to the virtualization module; a second failure monitoring module for detecting a failure in the virtual machine; and a second memory dump module for copying, to the external apparatus, a second area in the memory which is allocated by the virtualization module to the virtual machine.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: February 19, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Keiichi Matsuzawa, Noboru Morishita, Toshiomi Moriki
  • Patent number: 10114667
    Abstract: In a method of controlling a communication path among a plurality of virtual machines operating in one or more physical machines each of which includes one or more CPUs, memories, and I/O devices, allocating a virtual buffer serving as an alias of an actual buffer of a first virtual machine to a communication port that serves as a destination to which a communication path is changed from the first virtual machine and a second virtual machine directly or indirectly communicates with using a communication path change instruction as a trigger. Then, performing memory address translation on a region of the memory referred to by the virtual buffer, and generating the communication path between the first virtual machine and the second virtual machine by associating a region of the memory referred to by the first virtual machine and a region of the memory referred to by the second virtual machine.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: October 30, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiko Mizuno, Toshiomi Moriki, Takayuki Imada
  • Publication number: 20180307518
    Abstract: A machine system includes a physical machine, a memory pool, and a memory pool management machine. The memory pool management machine manages, with respect to a memory region of the memory pool, an allocated region, a cleared region, and an uncleared region. When generating a virtual machine, a hypervisor in the physical machine sends a memory allocation request to the memory pool management machine. When a response, to the request, received from the memory pool management machine includes an address range belonging to the uncleared region, the hypervisor clears the memory region of the address range belonging to the uncleared region and then generates the virtual machine.
    Type: Application
    Filed: January 8, 2016
    Publication date: October 25, 2018
    Inventors: Takayuki IMADA, Toshiomi MORIKI
  • Publication number: 20180203805
    Abstract: A computer on which OSs run is coupled to the storage apparatus, the OSs include a first OS controlling access to the storage apparatus and a second OS generating a virtual computer. A logically divided computer resources are allocated to the first OS and the second OS respectively. A third OS for executing an application runs on the virtual computer. The second OS has a shared region management part managing a shared region that is a memory region used for communication between the application and the first OS. The third operating system has an agent requesting the second operating system to secure the shared region based on a request from the application and mapping the secured shared region to a guest virtual address space.
    Type: Application
    Filed: July 8, 2015
    Publication date: July 19, 2018
    Applicant: HITACHI, LTD.
    Inventors: Yukari HATTA, Norimitsu HAYAKAWA, Takao TOTSUKA, Toshiomi MORIKI, Satoshi KINUGAWA
  • Publication number: 20170277632
    Abstract: A hypervisor that allocates the computer resource of a physical computer to one or more logical partitions allocates the computer resource to be allocated to the logical partitions to the logical partitions; generates, as address conversion information, the relationship between a guest physical address and a host physical address with respect to a memory of the computer resource; enables a first address conversion portion of a processor using the address conversion information; disables the first address conversion portion after the starting of a guest OS is completed; and causes an application to be executed.
    Type: Application
    Filed: October 30, 2014
    Publication date: September 28, 2017
    Applicant: Hitachi, Ltd.
    Inventors: Toshiomi MORIKI, Naoya HATTORI, Takayuki IMADA
  • Publication number: 20170277587
    Abstract: A computer system, having: a physical computer, which includes a processor and a memory; and an external apparatus, which is coupled to the physical computer and which includes a storage apparatus, the physical computer further includes: a virtualization module for providing at least one virtual machine; a first failure monitoring module for detecting a failure in the physical computer and the virtualization module; a first memory dump module for copying, to the external apparatus, a first area in the memory which is allocated to the virtualization module; a second failure monitoring module for detecting a failure in the virtual machine; and a second memory dump module for copying, to the external apparatus, a second area in the memory which is allocated by the virtualization module to the virtual machine.
    Type: Application
    Filed: October 8, 2014
    Publication date: September 28, 2017
    Inventors: Keiichi MATSUZAWA, Noboru MORISHITA, Toshiomi MORIKI
  • Patent number: 9697024
    Abstract: A first processor group of physical processors having hardware-assisted virtualization set disabled among the plurality of physical processors; a second processor group of physical processors having the hardware-assisted virtualization set enabled among the plurality of physical processors; a first OS to which the first processor group is allocated; and a virtualization part to which the second processor group is allocated, the virtualization part is configured to: allocate a predetermined area within the memory and a predetermined one of the plurality of physical processors within the second processor group to the second OS as the virtualized processor, and boot the second OS to be provided as the virtual machine; and set a shared area, which is readable/writable by both the first OS and the virtualization part, and set interrupt routing information comprising a correspondence relationship between a logical interrupt to the second OS and a physical interrupt thereto.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: July 4, 2017
    Assignee: HITACHI, LTD.
    Inventors: Takayuki Imada, Toshiomi Moriki, Naoya Hattori
  • Publication number: 20170123835
    Abstract: In a method of controlling a communication path among a plurality of virtual machines operating in one or more physical machines each of which includes one or more CPUs, memories, and I/O devices, allocating a virtual buffer serving as an alias of an actual buffer of a first virtual machine to a communication port that serves as a destination to which a communication path is changed from the first virtual machine and a second virtual machine directly or indirectly communicates with using a communication path change instruction as a trigger. Then, performing memory address translation on a region of the memory referred to by the virtual buffer, and generating the communication path between the first virtual machine and the second virtual machine by associating a region of the memory referred to by the first virtual machine and a region of the memory referred to by the second virtual machine.
    Type: Application
    Filed: August 23, 2016
    Publication date: May 4, 2017
    Inventors: Kazuhiko MIZUNO, Toshiomi MORIKI, Takayuki IMADA
  • Patent number: 9639486
    Abstract: A computer, having: a first OS to which a first processor core group is allocated; and a virtualization module to which a second processor core group is allocated, wherein a virtualization module registers interrupt handler processing for resetting the second processor core group, wherein a first OS has: a monitoring module for monitoring the virtualization module; and an interrupt control module for obtaining identifiers of the second processor core group at a time of booting of the virtualization module, and, when the monitoring module determines to reboot the virtualization module, issuing resetting interrupt to the processor cores of the second processor core group that are associated with the kept identifiers, wherein the second processor core group receives the resetting interrupt and executes the interrupt handler processing to reset its own processor cores, wherein the interrupt control module issues startup interrupt to the second processor core group.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: May 2, 2017
    Assignee: HITACHI, LTD.
    Inventors: Takayuki Imada, Toshiomi Moriki
  • Patent number: 9495172
    Abstract: A computer system with a plurality of processors having a hardware-assisted virtualization and a memory, the computer system including a first processor group of the processors having hardware-assisted virtualization set disabled, and a second processor group of the processors and having hardware-assisted virtualization set enabled, the method having: booting a first OS by assigning the first processor group to the first OS; booting a virtual machine monitor to boot a virtual machine by assigning the second processor group to the virtual machine monitor; performed by the virtual machine monitor, booting a second OS by assigning a certain area of the memory to the second OS; and performed by the virtual machine monitor, setting a data path through which the first OS and second OS communicate with each other, the data path being set in the memory.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: November 15, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Toshiomi Moriki, Takayuki Imada, Naoya Hattori
  • Patent number: 9396013
    Abstract: A next-generation OS with a virtualization feature is executed as a user program on a first virtual processor by selecting, in response to a cause of a call for a host VMM, one of a guest status area (221) for executing a user program on a second virtual processor and a host status area (222) for executing the guest VMM, and by updating a guest status area (131) of a shadow VMCS for controlling a physical processor. Accordingly, without a decrease in performance of a virtual computer, the next-generation OS incorporating the virtualization feature is executed on a virtual server, and the next-generation OS and an existing OS are integrated on a single physical computer.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: July 19, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Toshiomi Moriki, Naoya Hattori, Yuji Tsushima
  • Patent number: 9397886
    Abstract: In a multi-tenancy information processing system, a necessary setting change item and a target NW device are specified at the time of changing a configuration of a virtual machine of a tenant. A management server 116 includes a device management table 352 for each tenant and each segment, in which an NW setting item set for a network (NW) device is stored for each of the NW devices corresponding to the segment of the tenant, in advance. The management server 116 receives a configuration change request including type information on a request representing addition, deletion, or movement of the virtual machine, an identifier of a target tenant, and an identifier of a target segment.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: July 19, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiko Yasuda, Toshiomi Moriki, Susumu Takase
  • Patent number: 9361124
    Abstract: A computer system comprising a plurality of computers on which a plurality of operating systems run, wherein a memory stores a first hardware control unit, wherein a storage device stores a first OS image, a second OS image, a second hardware control unit for executing start processing of the second OS, and an address rewrite unit, wherein the second hardware control unit includes a start unit for starting the second hardware control unit, wherein the address rewrite unit which is started by the first OS is configured to: obtain an address of a storage area, in which address data to be rewritten is stored, as a target address, rewrite the address data stored in the storage area corresponding to the obtained target address and start the start unit, wherein the start unit is configured to start the second hardware control unit by using the rewritten address data.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: June 7, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Norimitsu Hayakawa, Keisuke Yoshida, Takashi Shimojo, Masatoshi Konagaya, Yoshihito Nakagawa, Toshiomi Moriki
  • Patent number: 9304794
    Abstract: Provided is a virtual machine including a first virtualization module operating on a physical CPU, for providing a first CPU, and a second virtualization module operating on the first CPU, for providing second CPU. The second virtualization module includes first processor control information holding a state of the first CPU obtained at a time of execution of the user program. The first virtualization module includes second processor control information containing a state of the physical CPU obtained at the time of the execution of the second virtualization module, third processor control information containing a state of the physical CPU obtained at the time of the execution of the user program, and prefetch entry information in which information to be prefetched from the third processor control information is set, and, upon detection of a event, the information set in the prefetch entry information is reflected to the first processor control information.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: April 5, 2016
    Assignee: HITACHI, LTD.
    Inventors: Toshiomi Moriki, Naoya Hattori, Yuji Tsushima
  • Patent number: 9207939
    Abstract: There is a need for providing the Xeon CPU with a two-level VM that is independent of VMM types and prevents the throughput from degrading when the OS operates the privilege register. A machine is provided with a processor and memory. The machine includes a first virtual machine manager for managing a virtual machine, a second virtual machine for managing an operating system, first management information, and second management information. The processor is provided with a register and a shadowing function. The machine uses a virtualization method. The first virtual machine manager detects a call from the second virtual machine manager. The first virtual machine manager enables the shadowing function when it is determined that an instruction for enabling the shadowing function caused the call.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: December 8, 2015
    Assignee: HITACHI, LTD.
    Inventors: Naoya Hattori, Toshiomi Moriki, Yoshiko Yasuda
  • Patent number: 9176806
    Abstract: In a memory inspection in a computer installing a x86 CPU, system software related to low-frequent processing is prevented from going down, and the suppression of performance degradation and the avoidance of a reduction in memory capacity by the memory inspection is realized. The computer having a processor, a memory, and an I/O device. The memory stores a system software realizing a system control unit, and an inspection program realizing an inspection unit. The processor has a memory fault notifying unit notifying the system control unit of a fault address. The system control unit includes an adjustment unit that determines whether the inspection program needs to be executed, or not, based on the type of event occurring, plural event processing units processing the event by using different storage areas of the memory, a fault recording unit recording the memory fault, and an event processing unit selector.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: November 3, 2015
    Assignee: HITACHI, LTD.
    Inventors: Naoya Hattori, Toshiomi Moriki