Patents by Inventor Toshiomi Moriki

Toshiomi Moriki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7734893
    Abstract: A method is provided which eliminates redundancy from the shadow PT operation performed by the virtual machine monitor (VMM) when the guest operating system running on a virtual machine updates a guest page table (PT) address. The VMM associates a plurality of shadow PTs with guest PTs and allocates their relation in memory. When it detects the update of a guest PT address, the VMM searches for a shadow PT corresponding to the updated guest PT. If the associated shadow PT exists, the VMM omits rewriting the shadow PT and registers the address of the shadow PT with the central processing unit (CPU). If the associated shadow PT does not exist, the VMM allocates a memory, creates a shadow PT, registers an address of the created shadow PT with the CPU, and records a relationship between the updated guest PT and the generated shadow PT.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: June 8, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Naoya Hattori, Toshiomi Moriki, Yuji Tsushima
  • Publication number: 20100138208
    Abstract: A VMM disables an interrupt interception flag on at least one CPU to execute, upon reception of an interrupt, an interrupt handler code of an OS, and enables the interrupt interception flag on the at least one CPU to execute, upon the reception of the interrupt, an emulator in the VMM. When, to a virtual machine, an I/O device is assigned in a dedicated form, and when the CPU is assigned while the interrupt interception is disabled, a destination of the interrupt from the physical I/O device is set to the corresponding CPU on which the interrupt interception is disabled. When, to the virtual machine, the I/O device is assigned in a shared form, or when the CPU is assigned while the interrupt interception is disabled, the destination of the interrupt from the physical I/O device is set to the corresponding CPU on which the interrupt interception is enabled.
    Type: Application
    Filed: November 24, 2009
    Publication date: June 3, 2010
    Inventors: Naoya HATTORI, Toshiomi Moriki, Takashige Baba, Yuji Tsushima
  • Patent number: 7725642
    Abstract: This invention provides a program product for a virtual computer that partitions a physical computer into a plurality of logical partitions through a hypervisor and runs an OS on each of the logical partitions, the program product including: a procedure (S1) of detecting an exception or an interruption occurring in the physical computer; a procedure (S2) of identifying an OS on a logical partition where the detected exception or interruption occurring; a procedure (S4) of copying a given storage area that contains an instruction that is the subject of the exception or interruption from a storage area where the identified OS is stored to a storage area that is managed by the hypervisor; a procedure (S6) of replacing, in the copied storage area, the exception or interruption subject instruction with an instruction that substitutes for the exception or interruption subject instruction; and a procedure (S7) of moving a location where the physical computer executes an instruction to the copied storage area.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: May 25, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Tsushima, Toshiomi Moriki, Naoya Hattori
  • Publication number: 20100115513
    Abstract: Provided is a virtual machine including a first virtualization module operating on a physical CPU, for providing a first CPU, and a second virtualization module operating on the first CPU, for providing second CPU. The second virtualization module includes first processor control information holding a state of the first CPU obtained at a time of execution of the user program. The first virtualization module includes second processor control information containing a state of the physical CPU obtained at the time of the execution of the second virtualization module, third processor control information containing a state of the physical CPU obtained at the time of the execution of the user program, and prefetch entry information in which information to be prefetched from the third processor control information is set, and, upon detection of a event, the information set in the prefetch entry information is reflected to the first processor control information.
    Type: Application
    Filed: October 30, 2009
    Publication date: May 6, 2010
    Inventors: Toshiomi MORIKI, Naoya Hattori, Yuji Tsushima
  • Publication number: 20100082874
    Abstract: In order to provide an inexpensive way to share an I/O device loaded in an I/O drawer among a plurality of blades, in a server system including a plurality of servers, a PCI device, and a manager for initializing a PCI switch, the PCI device has a plurality of virtual functions (VFs). The PCI switch, which has VF allocation information which indicates association between the servers and the VFs, is configured to: receive a transaction from one of the servers or from the PCI device; when the received transaction is a transaction sent from the one of the servers, remove a server identifier with which a sender server is identified and transfer the received transaction to the PCI device; and when the received transaction is a transaction sent from the PCI device, attach a server identifier that is determined based on the VF allocation information.
    Type: Application
    Filed: August 24, 2009
    Publication date: April 1, 2010
    Inventors: Takashige BABA, Toshiomi Moriki, Keitaro Uehara
  • Publication number: 20100017643
    Abstract: Provided is a failover method for a cluster system for realizing smooth failover of the guest OS's, even when there are many guest OS's, while reducing consumption of computer resources of a server. Smooth failover is realized by preventing competition during failover even when the number of guest OS's is increased. In a cluster configuration in which a slave/master cluster program is operated in a guest OS/host OS, the master cluster program (510) collects and transmits heartbeats of the slave cluster program, thereby realizing failure monitoring through the certain amount of heartbeats without depending on the number of guest OS's. Further, when the master cluster program monitors failures of the slave cluster program of its own computer to find a normal operation of the guest OS, the amount of communication through heartbeats is reduced by eliminating the necessity of communication to a standby system slave cluster program.
    Type: Application
    Filed: September 23, 2009
    Publication date: January 21, 2010
    Inventors: Tsunehiko Baba, Yuji Tsushima, Toshiomi Moriki
  • Patent number: 7617411
    Abstract: Provided is a failover method for a cluster system for realizing smooth failover of the guest OS's, even when there are many guest OS's, while reducing consumption of computer resources of a server. Smooth failover is realized by preventing competition during failover even when the number of guest OS's is increased. In a cluster configuration in which a slave/master cluster program is operated in a guest OS/host OS, the master cluster program (510) collects and transmits heartbeats of the slave cluster program, thereby realizing failure monitoring through the certain amount of heartbeats without depending on the number of guest OS's. Further, when the master cluster program monitors failures of the slave cluster program of its own computer to find a normal operation of the guest OS, the amount of communication through heartbeats is reduced by eliminating the necessity of communication to a standby system slave cluster program.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: November 10, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Tsunehiko Baba, Yuji Tsushima, Toshiomi Moriki
  • Publication number: 20090216913
    Abstract: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed.
    Type: Application
    Filed: April 29, 2009
    Publication date: August 27, 2009
    Inventors: Toshiomi Moriki, Keitaro Uehara, Yuji Tsushima
  • Patent number: 7577864
    Abstract: Provided is a technology for increasing reliability of communication carried out by OSes and application programs operating on logical partitions set on a computer. The computer has multiple logical partitions constructed therein by a control program, the physical interfaces are shared by virtual interfaces respectively set for the multiple logical partitions, and the memory module stores management information indicating correspondences between the physical interface and the virtual interface.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: August 18, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhide Horimoto, Toshiomi Moriki, Yuji Tsushima, Takuichi Hoshina
  • Publication number: 20090150896
    Abstract: Provided is a method of controlling a virtual computer system in which a physical computer includes a plurality of physical CPUs that is switchable between a sleep state and a normal state, and a virtualization control unit divides the physical computer into a plurality of logical partitions to run a guest OS in each of the logical partitions and controls allocation of resources of the physical computer to the logical partitions, causes the virtualization control unit to: receive an operation instruction for operating the logical partitions; and if the operation instruction is for deleting a virtual CPU from one of the logical partitions, delete this virtual CPU from a table for managing virtual CPU-physical CPU allocation and put, if the deleting leaves no virtual CPUs allocated to one of the physical CPUs that has been allocated the deleted virtual CPU, this one of the physical CPUs into the sleep state.
    Type: Application
    Filed: December 4, 2008
    Publication date: June 11, 2009
    Inventors: Yuji TSUSHIMA, Keitaro UEHARA, Toshiomi MORIKI, Naoya HATTORI
  • Patent number: 7539788
    Abstract: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: May 26, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Toshiomi Moriki, Keitaro Uehara, Yuji Tsushima
  • Publication number: 20090007112
    Abstract: A next-generation OS with a virtualization feature is executed as a user program on a first virtual processor by selecting, in response to a cause of a call for a host VMM, one of a guest status area (221) for executing a user program on a second virtual processor and a host status area (222) for executing the guest VMM, and by updating a guest status area (131) of a shadow VMCS for controlling a physical processor. Accordingly, without a decrease in performance of a virtual computer, the next-generation OS incorporating the virtualization feature is executed on a virtual server, and the next-generation OS and an existing OS are integrated on a single physical computer.
    Type: Application
    Filed: June 17, 2008
    Publication date: January 1, 2009
    Inventors: Toshiomi Moriki, Naoya Hattori, Yuji Tsushima
  • Publication number: 20080307180
    Abstract: The program attains compatibility of suppression of an overhead accompanying page exception handling in the case of operating a program whose amount of memory use is large on a virtual machine and suppression of the overhead accompanying page exception handling in the case of operating a first OS that has a function of making another OS run on a virtual machine. A VMM creates a shadow PT for prohibiting reading-writing of privileged memory that requires emulation of reading/writing by using a RSV-bit, and registers the shadow PT and the second PT that a second OS operating on the first OS has in an x86 compatible CPU equipped with a page exception detecting function using two PT's. When a page exception occurs, the VMM refers to a cause code of the page exception and, when a P field of the cause code is 0, determines immediately that emulation is unnecessary.
    Type: Application
    Filed: February 13, 2008
    Publication date: December 11, 2008
    Inventors: Naoya HATTORI, Toshiomi Moriki, Yuji Tsushima
  • Publication number: 20080263390
    Abstract: Even when a large number of guest OSs exist, a failover method meeting high availability needed by the guest OSs is provided for the each guest OS. In the event of a physical or logical change of a system, or change of operation states, a smooth failover method can be realized by preventing the consumption of resource amounts due to excessive failover methods, and the occurrence of systemdown due to an inadequate failover method. In a server virtualization environment, in a cluster configuration having a failover method due to hot standby and cold standby, by selecting a failover method meeting high availability requirements specifying performance during failover of applications on the guest OSs, a suitable cluster configuration is realized. Failure monitoring is realized by quantitative heartbeat.
    Type: Application
    Filed: August 3, 2007
    Publication date: October 23, 2008
    Inventors: Tsunehiko Baba, Toshiomi Moriki, Yuji Tsushima
  • Publication number: 20080172499
    Abstract: The present invention provides a machine system that enables the arbitration of IO accesses and band control based on the priority of virtual servers while curbing performance overhead during IO sharing among the virtual servers. A virtual machine system including a CPU, a memory, and an IO interface includes a hypervisor that generates plural virtual servers, and an IO controller that controls the IO interface. The IO controller includes: a DMA receiving unit that receives DMA requests from the IO interface; a decoder that decodes received DMA requests and locates the corresponding virtual servers; a DMA monitoring counter that monitors DMA processing status for each of the virtual servers; a threshold register set in advance for each of the virtual servers; and a priority deciding unit that compares the DMA monitoring counter and the value of the threshold register, and based on processing priority obtained as a result of the comparison, decides the priority of processing of the received DMA requests.
    Type: Application
    Filed: June 29, 2007
    Publication date: July 17, 2008
    Inventors: Toshiomi MORIKI, Keitaro Uehara, Yuji Tsushima
  • Publication number: 20080162983
    Abstract: Provided is a failover method for a cluster system for realizing smooth failover of the guest OS's, even when there are many guest OS's, while reducing consumption of computer resources of a server. Smooth failover is realized by preventing competition during failover even when the number of guest OS's is increased. In a cluster configuration in which a slave/master cluster program is operated in a guest OS/host OS, the master cluster program (510) collects and transmits heartbeats of the slave cluster program, thereby realizing failure monitoring through the certain amount of heartbeats without depending on the number of guest OS's. Further, when the master cluster program monitors failures of the slave cluster program of its own computer to find a normal operation of the guest OS, the amount of communication through heartbeats is reduced by eliminating the necessity of communication to a standby system slave cluster program.
    Type: Application
    Filed: February 20, 2007
    Publication date: July 3, 2008
    Inventors: Tsunehiko Baba, Yuji Tsushima, Toshiomi Moriki
  • Publication number: 20080162734
    Abstract: When the entire system is split into plural partitions on chipsets connecting plural processors, IO hubs, and memory controllers, and an OS is operating on each of the partitions, the present invention prevents a failure in a partition from propagating to other partitions. Based on address information or issuer information included in a packet inputted to a chipset, a partition from which the packet was issued is identified, and an identified partition identifier is added to the packet. Based on the added partition identifier, a partition initializing part selectively deletes the packet issued from the partition in which a failure occurred, thereby preventing the influence of the failure in the failure-causing partition from propagating to other partitions.
    Type: Application
    Filed: June 27, 2007
    Publication date: July 3, 2008
    Inventors: Keitaro UEHARA, Toshiomi Moriki, Yuji Tsushima
  • Publication number: 20070234358
    Abstract: Provided is the virtual computer system including an emulation module for emulating an operation based on an operation code for executing the operation of hardware of a server system, an exception event handler module for calling the emulation module when an exception event is generated by a CPU, a code management module for managing a promotion code for emulating the operation of the hardware of the server system, a frequency judgment module for judging whether a frequency of the operation of the hardware of the server system is high, and a switching module for determining whether to call the emulation module by the exception event handler module or to call the emulation module by executing the promotion code based on the judged frequency. Accordingly, the virtual computer system can simultaneously achieve high performance and memory saving in an emulation system.
    Type: Application
    Filed: February 8, 2007
    Publication date: October 4, 2007
    Inventors: Naoya Hattori, Toshiomi Moriki, Yuji Tsushima
  • Publication number: 20070192459
    Abstract: Provided is a technology for increasing reliability of communication carried out by OSes and application programs operating on logical partitions set on a computer. The computer has multiple logical partitions constructed therein by a control program, the physical interfaces are shared by virtual interfaces respectively set for the multiple logical partitions, and the memory module stores management information indicating correspondences between the physical interface and the virtual interface.
    Type: Application
    Filed: September 1, 2006
    Publication date: August 16, 2007
    Inventors: Kazuhide Horimoto, Toshiomi Moriki, Yuji Tsushima, Takuichi Hoshina
  • Publication number: 20070162683
    Abstract: A method is provided which eliminates redundancy from the shadow PT operation performed by the VMM when the guest operating system running on a virtual machine updates a guest PT address. The VMM associates a plurality of shadow PTs with guest PTs and allocates their relation in memory. When it detects the update of a guest PT address, the VMM searches for a shadow PT corresponding to the updated guest PT. If the associated shadow PT exists, the VMM omits rewriting the shadow PT and registers the address of the shadow PT with the CPU. If the associated shadow PT does not exist, the VMM allocates a memory, creates a shadow PT, registers an address of the created shadow PT with the CPU, and records a relationship between the updated guest PT and the generated shadow PT.
    Type: Application
    Filed: January 10, 2007
    Publication date: July 12, 2007
    Inventors: Naoya Hattori, Toshiomi Moriki, Yuji Tsushima