Abstract: A method and a system for bidirectional transmission/reception of data between two terminal stations, in which each transmission period is divided into a plurality of first time sections for relatively low speed data transmission and at least one second time section for relatively high speed data transmission, the direction of transmission between the terminal stations being predetermined in each of the first time sections, while the direction of transmission between the terminal stations is reversible in each of the second time sections, each second time section being preceded by one of the first time sections. Transmission of information data and control data is performed from one to the other terminal station in a predetermined direction in each first time section, and the direction of data transmission between the terminal stations in the next second time section is determined on the basis of control data contained in the relatively low speed data transmission.

Abstract: A switched-capacitor filter of the present invention constituted in the form of a semiconductor integrated circuit has an input circuit which consists of at least one noninversion-type switched-capacitor and at least two inversion-type switched-capacitors that are connected in parallel with each other. The two inversion-type switched-capacitors have different writing timings and reading timings relative to each other. With this setup, capacitances of the switched-capacitors need not be extremely increased even when it is desired to maintain a zero-point frequency of the filter at a very low value. Further, there is no need of providing a circuit such as sample holding circuit which requires extra area and consumes additional electric power.

Abstract: A method of producing and applying a cement-containing composition such as a concrete and mortar broadly used in civil, construction and various other fields is disclosed. To prepare the mortar or the like, a hydration reaction of cement and water is caused in the presence, if necessary, of aggregate such as sand or gravel. According to the present invention, small ice masses are used in lieu of water. That is, cement, aggregate and small ice masses are mixed and kneaded together in a low water-cement ratio and in a quasisolid state wetted by a small quantity of water resulting on the surfaces of the small ice masses from the melting thereof into a macroscopically homogeneous system. Subsequently, gradual transition of this system into a homogeneous mixture with the melting of the small ice masses is caused. The ice masses are entirely melted until the instant of charging of the composition thus prepared.

Abstract: A system in which two stations are respectively provided with telephones and data terminals such that a voice and data are multiplexed for communication between the two stations. Each station has a circuit to convert voice signals inputted from the telephone into a plurality of kinds of predetermined voice parameters, a circuit to determine a transmission mode depending on a predetermined parameter of the voice signals, a circuit to extract data having a length corresponding to the transmission mode from data to be transmitted from the data terminal, a circuit to select one of the plurality of voice parameters depending on the transmission mode, and a unit to edit a mode indicator indicating the transmission mode, the selected voice parameter, and the extracted data into a transmission block format corresponding to the transmission mode.

Abstract: In a waveform differential type timing phase detector circuit, phase information available from the timing phase detector circuit is made valid for use as control information only when the input pulse assumes a specified pattern, in order to detect a timing phase signal removal of jitters due to waveform distortion.

Abstract: A switched-capacitor filter constituted in the form of a semiconductor integrated circuit has an input circuit which consists of at least one noninversion-type switched-capacitor and at least two inversion-type switched-capacitors that are connected in parallel with each other. The two inversion-type switched-capacitors have different writing timings and reading timings relative to each other. With this setup, capacitances of the switched-capacitors need not be extremely increased even when it is desired to maintain a zero-point frequency of the filter at a very low value. Further, there is no need of providing a circuit such as sample holding circuit which requires extra area and consumes additional electric power.

Abstract: A method of preparing and molding a hydraulic cement-containing composition such as concrete or mortar is disclosed, which can be extensively utilized in the fields of civil engineering, construction projects, or the like. In the preparation of a hydraulic cement-containing composition, cement and water, and sand, gravel or the like, if necessary, are kneaded together to cause the hydration reaction. A feature of the present invention resides in preparing a mortar or the like containing water necessary for the hydration reaction in the form of ice pieces and causing the hydration of cement and water to result from the melting of the ice pieces.

Abstract: An integrated circuit is constructed in order that tests can be conducted on a plurality of circuits to determine which of the circuits is defective. In particular, the circuit is constructed to allow such testing with the use of fewer input and output pins for testing. To accomplish this, a first buffer gate circuit, a resistor, and a second buffer gate are connected in series in the order mentioned between the output terminal of a first circuit and the input terminal of a second circuit. An input and output terminal pin for testing is located at a junction point of the resistor and second buffer gate.

Abstract: A timing signal extraction circuit has a clock signal extractor for extracting from a transmitted data signal a clock component synchronous with the transmission rate of the transmitted signal, an oscillator having an oscillation frequency about M (M: an integer) times as high as the transmission rate of the transmitted signal, a phase-locked loop detecting the phase difference between the output signal of a frequency divider frequency-dividing the output signal of the oscillator and the output signal of the clock signal extractor thereby controlling the operating phase of the oscillator, and a logic circuit producing a plurality of pulse trains whose bit rate is equal to the transmission rate of the transmitted signal and which have respectively different phases. A pulse train having a desired phase is selected from among the plural pulse trains to provide a decision timing signal.

Abstract: For realizing a stabilized current source circuit providing a stabilized current which is insensitive to a change in the threshold voltage of a MOS transistor, a gate electrode of a first MOS transistor feeding a drain current as a constant current output is supplied with the sum of the gate-source voltage of a second MOS transistor and the potential of a stabilized voltage source.

Abstract: In an interface circuit which couples a two-wire line of bidirectional transmission and unidirectional four-wire receiving and transmitting lines; in order to permit the interface circuit to operate in adaptation to the fluctuation of an impedance with the two-wire line side viewed from the four-wire receiving line, the four-wire receiving line is provided with a plurality of filters and a group of switches for selecting the filters, an output of the four-wire transmitting line is compared with outputs obtained by scanning the filters, and the filter providing the minimum output difference in the comparisons is selected and connected.

Abstract: A differential amplifier formed of MISFETs includes a differential amplification stage and a pair of cascade amplification stages which receive outputs from the differential amplification stage. In each of the cascade amplification stages, an amplifying MISFET which receives an input signal at its source has a channel conductivity of opposite type to that of the differential input MISFETs of the differential amplification stage. The differential amplifier with this construction has good frequency characteristics. Since the pair of cascade amplification stages make the currents taken from a pair of outputs from the differential amplification stage equal to each other, the operating balance of the differential amplification stage is not affected.

Abstract: A line equalizer including a .sqroot.f equalizer for compensating a .sqroot.f-characteristic of a transmission line, a BT equalizer connected in series with the .sqroot.f equalizer for removing an echo component caused by a bridged tap (namely, BT) on the transmission line, and a circuit for controlling the .sqroot.f equalizer is disclosed. A signal applied to the .sqroot.f equalizer is subjected to over-equalization to make the time domain length of impulse response at the output of the .sqroot.f equalizer small. The equalization state of the output of the .sqroot.f equalizer is judged by signals formed in the BT equalizer, and the gain of the .sqroot.f equalizer is controlled on the basis of the result of judgement. In this manner, the .sqroot.f equalizer is controlled without suffering any interference between a control loop of the .sqroot.f equalizer and a control loop of the BT equalizer.

Abstract: A small-sized LSI variable equalizer is provided for accurately equalizing waveforms of signals transmitted via transmission lines of different distances. Variable equalizer units capable of stepwise changing the equalizing characteristics thereof are connected in series with each other with the variable equalizer units having variable step widths different from each other. An output signal of the variable equalizer units is compared with a reference signal to convert the comparison output signal to a digital signal which includes an upper order bits and lower order bits, whereby one of the equalizer units which has a wide variable step width is controlled by the upper order bits and the other of the equalizer units which has a narrow variable step width is controlled by the lower order bits.

Abstract: An interpolation or smoothing filter circuit for a switched-capacitor system which transforms the sampled-and-held output signals from a switched-capacitor filter into sampled-and-held signals with a doubled sample rate. The circuit comprises an operational amplifier whose noninverting input lead is connected to a switched capacitor network which receives the sampled-and-held input signals at the normal sample rate. The network includes two separate capacitors controlled by switches operable at two alternating clock phases and connected to provide the desired summation and holding of charges. Feedback leads connected between the amplifier output lead and its noninverting input lead and containing additional capacitors cooperate with the input network to produce an output signal that is sampled-and-held at twice the sample rate of the input signal.

Abstract: A switched-capacitor cosine filter for a sampled-data system functions to reject extraneous frequency components of an incoming analog signal around the sampling frequency, thereby avoiding aliasing. The filter comprises an operational amplifier whose inverting input receives input signals through a switched input capacitor controlled by a four-switch network controlled by alternating clock phases and feedback signals from the amplifier output through a feedback capacitor. The transfer function of the circuit provides a zero of transmission at the sampling frequency, thereby eliminating unwanted frequency components. A self-contained version of the cosine filter is provided by the addition of another grounded switched capacitor with appropriately timed switches in the feedback network.