Patents by Inventor Toshiya Kotani

Toshiya Kotani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140242498
    Abstract: According to one embodiment, a production method for a mask layout of an exposure mask includes evaluating a candidate layout by comparison between an imaged image group and a reference image group. The imaged image group is composed of a plurality of imaged images of patterns formed by performing lithography under a plurality of levels of exposure condition using the candidate layout. The reference image group is composed of a plurality of reference images produced by simulation on assumption of a plurality of levels of the exposure condition.
    Type: Application
    Filed: August 29, 2013
    Publication date: August 28, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuko Kono, Kazuyuki Masukawa, Toshiya Kotani, Chikaaki Kodama, Yasunobu Kai
  • Patent number: 8809072
    Abstract: According to a sub-resolution assist feature arranging method in embodiments, it is selected which of a rule base and a model base is set for which pattern region on pattern data corresponding to a main pattern as a type of the method of arranging the sub-resolution assist feature for improving resolution of the main pattern formed on a substrate. Then, the sub-resolution assist feature by the rule base is arranged in a pattern region set as the rule base and the sub-resolution assist feature by the model base is arranged in a pattern region set as the model base.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: August 19, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chikaaki Kodama, Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi
  • Publication number: 20140183702
    Abstract: According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion.
    Type: Application
    Filed: December 18, 2013
    Publication date: July 3, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Chikaaki KODAMA, KOICHI NAKAYAMA, TOSHIYA KOTANI, SHIGEKI NOJIMA, FUMIHARU NAKAJIMA, HIROTAKA ICHIKAWA
  • Publication number: 20140131879
    Abstract: According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion.
    Type: Application
    Filed: January 15, 2014
    Publication date: May 15, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Chikaaki KODAMA, Koichi NAKAYAMA, Toshiya KOTANI, Shigeki NOJIMA, Fumiharu NAKAJIMA, Hirotaka ICHIKAWA
  • Publication number: 20140059502
    Abstract: According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected.
    Type: Application
    Filed: March 13, 2013
    Publication date: February 27, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Seiro MIYOSHI, Taiki KIMURA, Hiromitsu MASHITA, Fumiharu NAKAJIMA, Tetsuaki MATSUNAWA, Toshiya KOTANI, Chikaaki KODAMA
  • Publication number: 20140017887
    Abstract: According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)th second sidewall film matching a pattern of a nth (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2n)×(?/NA) or less when an exposure wavelength of an exposure device is ?, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.
    Type: Application
    Filed: September 12, 2013
    Publication date: January 16, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Fumiharu NAKAJIMA, Toshiya Kotani, Hiromitsu Mashita, Takafumi Taguchi, Ryota Aburada, Chikaaki Kodama
  • Patent number: 8617773
    Abstract: In the method of correcting a mask pattern according to the embodiments, a mask pattern correction amount for a reference flare value is calculated as a reference mask correction amount, for every type of patterns within the layout, and a change amount of the mask pattern correction amount corresponding to the change amount of the flare value is calculated as the change amount information. A mask pattern corresponding to the flare value of the pattern is created based on the reference mask correction amount and the change amount information corresponding to the pattern, extracted from the information having the pattern, the reference mask correction amount, and the change amount information correlated with each other, and based on a difference between the flare value of the pattern and the reference flare value.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: December 31, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taiga Uno, Toshiya Kotani, Hiromitsu Mashita, Yukiyasu Arisawa
  • Patent number: 8617999
    Abstract: A method of manufacturing a semiconductor device, which forms a pattern by performing pattern transformation steps multiple times, comprises setting finished pattern sizes for patterns to be formed in each consecutive two pattern transformation steps among the plurality of pattern transformation steps based on a possible total amount of in-plane size variation of the patterns to be formed in the consecutive two pattern transformation steps.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: December 31, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiromitsu Mashita, Toshiya Kotani, Fumiharu Nakajima, Takafumi Taguchi, Chikaaki Kodama
  • Patent number: 8609303
    Abstract: According to a mask pattern generating method of the embodiments, an undesired pattern, which is transferred onto a substrate due to an auxiliary pattern when an on-substrate pattern is formed on the substrate by using a mask pattern in which the auxiliary pattern is placed, is extracted as an undesired transfer pattern. Then, the mask pattern is corrected by changing a size of the auxiliary pattern according to a size and a position of the undesired transfer pattern.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: December 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chikaaki Kodama, Toshiya Kotani, Hiromitusu Mashita, Fumiharu Nakajima
  • Publication number: 20130241073
    Abstract: According to one embodiment, a semiconductor device includes a plurality of wires arranged in parallel at a predetermined pitch, a plurality at first contacts that are each connected to an odd-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to a wiring direction of the wires, and a plurality of second contacts that are each connected to an even-numbered wire among the wires and are arranged in parallel in an orthogonal direction with respect to the wiring direction of the wires in such a way as to be offset from the first contacts in the wiring direction of the wires, in which the first contacts are offset from the second contacts by a pitch of the wires in an orthogonal direction with respect to the wiring direction of the wires.
    Type: Application
    Filed: September 13, 2012
    Publication date: September 19, 2013
    Inventors: Takaki Hashimoto, Yasunobu Kai, Toshiya Kotani
  • Patent number: 8527914
    Abstract: A flare map calculating method of an embodiment calculates an optical image intensity distribution in each division region set in a pattern region. Furthermore, an average value of the optical image intensity distribution is calculated in each division region. A pattern or plural patterns, which has a pattern density corresponding to the average value, is calculated as a corresponding density pattern in each division region. Furthermore, a density map, which represents a pattern density distribution within the pattern region, is generated based on the corresponding density pattern, and a flare map representing a flare intensity distribution within the pattern region is calculated by convolution integral of the density map and a point spread function.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taiga Uno, Toshiya Kotani, Satoshi Tanaka
  • Publication number: 20130159944
    Abstract: A flare map calculating method of an embodiment calculates an optical image intensity distribution in each division region set in a pattern region. Furthermore, an average value of the optical image intensity distribution is calculated in each division region. A pattern or plural patterns, which has a pattern density corresponding to the average value, is calculated as a corresponding density pattern in each division region. Furthermore, a density map, which represents a pattern density distribution within the pattern region, is generated based on the corresponding density pattern, and a flare map representing a flare intensity distribution within the pattern region is calculated by convolution integral of the density map and a point spread function.
    Type: Application
    Filed: September 14, 2012
    Publication date: June 20, 2013
    Inventors: Taiga UNO, Toshiya KOTANI, Satoshi TANAKA
  • Publication number: 20130126959
    Abstract: According to one embodiment, there are provided a first shaped pattern in which a plurality of first holes are arranged and of which a width is periodically changed along an arrangement direction of the first holes, a second shaped pattern in which a plurality of second holes are arranged and of which a width is periodically changed along an arrangement direction of the second holes, and slits which are formed along the arrangement direction of the first holes and separate the first shaped pattern and the second shaped pattern.
    Type: Application
    Filed: September 13, 2012
    Publication date: May 23, 2013
    Inventors: Ryota Aburada, Takashi Obara, Toshiya Kotani
  • Patent number: 8443310
    Abstract: A pattern correcting method of an embodiment computes a distribution of pattern coverages on a design layout of a circuit pattern in the vicinity of a position that becomes an error pattern in a case where an on-substrate pattern is formed. Then, an area on the design layout in which a difference in the distribution of the pattern coverages becomes small by adding an addition pattern is set as an addition area. Next, addition pattern candidates to be added to the addition area are generated, an addition pattern to be added to the design layout is selected from the candidates on the basis of a predetermined selection criterion, and the addition pattern is added to the addition area.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: May 14, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masanari Kajiwara, Toshiya Kotani, Sachiko Kobayashi, Hiromitsu Mashita, Fumiharu Nakajima
  • Patent number: 8440376
    Abstract: According to one embodiment, a deviation amount distribution of a two-dimensional shape parameter between a mask pattern formed on a mask and a desired mask pattern is acquired as a mask pattern map. Such that a deviation amount of the two-dimensional shape parameter between a pattern on substrate formed when the mask is subjected to exposure shot to form a pattern on a substrate and a desired pattern on substrate fits within a predetermined range, an exposure is determined for each position in the exposure shot in forming the pattern on substrate based on the mask pattern map.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: May 14, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Kotani, Kazuya Fukuhara, Michiya Takimoto, Hidefumi Mukai, Soichi Inoue
  • Patent number: 8438527
    Abstract: According to one embodiment, an original plate evaluation method is disclosed. The original plate includes a substrate and N patterns differing from one another in shape. The method includes selecting N1 patterns from the N patterns based on first criterion, obtaining measured values for the N1 patterns, performing a decision whether the obtained measured values satisfy first specification value, selecting N2 patterns from the N patterns based on second criterion, predicting shapes of transfer patterns corresponding to N2 patterns, performing a decision whether the predicted shapes satisfy second specification value, and evaluating the plate based on the decision.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: May 7, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satomi Nakamura, Toshiya Kotani, Kazuhito Kobayashi, Akiko Mimotogi, Chikaaki Kodama
  • Publication number: 20130111416
    Abstract: According to one embodiment, a design data optimization method includes forming an angular aperture model, in first design data including a first and a second line patterns indicating an interconnect layout, based on an angular aperture between the first line pattern in which a conversion difference prediction point is set in a vertical direction and the second line pattern, and changing a distance between the first and second line patterns or a line width of the first and second line patterns in the first design data based on the angular aperture model and optimizing the first design data to second design data including the first and second line patterns changed.
    Type: Application
    Filed: March 22, 2012
    Publication date: May 2, 2013
    Inventors: Shinichi NAKAGAWA, Chikaaki Kodama, Kouichi Nakayama, Toshiya Kotani, Fumiharu Nakajima
  • Publication number: 20130063707
    Abstract: One embodiment includes: a step of evaluating an amount of flare occurring through a mask at EUV exposure; a step of providing a dummy mask pattern on the mask based on the evaluated result of the amount of flare; and a step of executing a flare correction and an optical proximity correction on a layout pattern. The layout pattern is provided by the EUV exposure through the mask with the dummy mask pattern.
    Type: Application
    Filed: March 15, 2012
    Publication date: March 14, 2013
    Inventors: Ryota ABURADA, Hiromitsu Mashita, Taiga Uno, Masahiro Miyairi, Toshiya Kotani
  • Publication number: 20130062771
    Abstract: According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion.
    Type: Application
    Filed: February 27, 2012
    Publication date: March 14, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Chikaaki KODAMA, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima
  • Publication number: 20130055172
    Abstract: According to one embodiment, an original plate evaluation method is disclosed. The original plate includes a substrate and N patterns differing from one another in shape. The method includes selecting N1 patterns from the N patterns based on first criterion, obtaining measured values for the N1 patterns, performing a decision whether the obtained measured values satisfy first specification value, selecting N2 patterns from the N patterns based on second criterion, predicting shapes of transfer patterns corresponding to N2 patterns, performing a decision whether the predicted shapes satisfy second specification value, and evaluating the plate based on the decision.
    Type: Application
    Filed: March 22, 2012
    Publication date: February 28, 2013
    Inventors: Satomi Nakamura, Toshiya Kotani, Kazuhito Kobayashi, Akiko Mimotogi, Chikaaki Kodama