Abstract: A semiconductor device includes an increase voltage generation circuit generating an increased voltage having a higher potential than a high potential of a power-supply voltage externally supplied. In the device, an increased voltage stabilizing capacitor is connected between the increased voltage and the high potential of the power-supply voltage, and stabilizes the increased voltage.

Abstract: A semiconductor memory device having a plurality of operating modes, and which offers improved operating speed without an increase in the chip surface area. The semiconductor memory device according to the present invention has access mode in which access is made in accordance with an external address signal, as well as at least one access mode in which access is performed of an internally generated address position, this semiconductor memory device further having a normal memory cell array, a redundancy memory cell array, a redundancy determining circuit which makes a determination of whether an address position to actually be accessed by a plurality of modes is an exchanged memory cell and which performs control so as to access that memory cell, a mode determining circuit which determines the mode, and an internal address generating circuit which internally and automatically generates an address position.

Abstract: A semiconductor device includes a plurality of signal lines, a plurality of first power lines for supplying electric power at a first voltage level, and a plurality of second power lines for supplying electric power at a second voltage level, wherein the signal lines, first power lines and the second power lines are disposed such that a signal line is laterally bounded by a first power line at a first side thereof and by another first power line at the other side thereof, a signal line different from the signal line that is bounded laterally by the first power lines, is laterally bounded by a second power line at a first side thereof and by another second power line at the other side thereof.

Abstract: The inputs of matching detection circuits 4i (i=0 to 3) is connected with each of one-bit data lines to one of a plurality of memory blocks 10 to 13, with its output connected to data terminal 2i. The input of distribution circuit 3i are connected to the data terminal 2i and its plurality of outputs, which are insulated from one another and output data corresponding to the data provided to the inputs are connected to the data lines that are connected to the inputs of the matching detection circuit 4i. A control circuit 16 that, during a data write in data compression test mode, invalidates the output from the matching detection circuit 4i to the data terminal 2i and validates outputs from the distribution circuit 3i to the data lines, and during a data read in the the data compression test mode, validates the output from the matching detection circuits 4i to the data terminal 2i and invalidates the outputs from the distribution circuits 3i to the data lines.

Abstract: A semiconductor memory device includes memory cells each having a depletion-type field effect transistor and a capacitor connected in series, a bit line connected to said memory cells, an amplifier unit for amplifying the potential of the bit line, and a voltage controlling unit for limiting a voltage applied to the bit line by the amplifier unit.

Abstract: An optical deflector is provided with a scanning mirror which is rotatable about a shaft and accompanied by a sleeve and hub. The pneumatic pressure around the mirror which is located within a cavity formed by a motor case of the deflector is maintained lower than an inside pneumatic pressure of a pneumatic pressure creation arrangement. The arrangement has the shaft provided with herringbone grooves engraved on the periphery thereof and the sleeve rotatable about the shaft together with the hub and the scanning mirror. When the scanning mirror rotates about the shaft, windage loss may be reduced, and when the inside pneumatic pressure between the shaft and the sleeve is kept higher than the atmospheric pressure, the rigidity of the shaft may be maintained during the rotation of scanning mirror about the shaft.

Abstract: A semiconductor memory device includes a flip-flop circuit, a switch provided between the flip-flop circuit and a pair of data lines, a write circuit writing data into the flip-flop circuit via the switch, and a circuit applying a predetermined voltage to the pair of data lines when the write circuit performs a write operation so that a voltage amplitude on the pair of data lines is limited so as to be less than a voltage amplitude of the flip-flop circuit in the write operation.

Abstract: A step-down circuit with a stabilized internal power supply in which the gate potential VG1 of an output transistor is controlled by the differential amplifying circuit so that the current flowing through the output transistor is increased/decreased when the internal power-supply potential is lowered/raised. The gate potential of the transistor which is varied as the variable current source of the differential amplifying circuit is controlled by the differential amplifying circuit so that the current flowing through the transistor is increased/decreased when the internal power-supply potential is lowered/raised in order to maintain a stabilized internal power supply.

Abstract: A semiconductor memory device includes first and second word lines which extend in parallel to each other, at least one line activation signal line which extends perpendicularly to the first and second word lines, a device isolation region which extends perpendicularly to the first and second word lines, a first driver for activating the first word line and having a first impurity region provided adjacent to the device isolation region and connected to the word line activation signal line, a first gate electrode and a second impurity region connected to the first word line, a second driver for activating the second word line and comprising a third impurity region provided adjacent to the device isolation region on an opposite side from the first impurity region and connected to the word line activation signal line, a second gate electrode and a fourth impurity region connected to the second word line, and a decoder connected to the first and second gate electrodes.

Abstract: A safety device for an engine cooling system having a heater core circuit for circulating the engine cooling water through the heater core of an automotive air conditioning system, and a radiator circuit for circulating the engine cooling water through a radiator. The safety device comprises a safety valve provided in the heater core circuit and capable of discharging the engine cooling water outside the vehicle when the temperature of the engine cooling water exceeds a predetermined temperature and/or when the pressure of the engine cooling water exceeds a predetermined pressure.

Abstract: A method of and apparatus for controlling automatic soldering system in which respective units of the automatic soldering system are controlled preparatorily to reduce the waiting time until main driving to zero. In the soldering driving time, the temperature of the work itself is precisely controlled to the predetermined value by means of directly measuring the temperature of the work and controlling the preheater to bring the soldering characteristic in the next soldering step into the most optimal value in compliance with the size and the like of the work to be soldered.