Abstract: A semiconductor memory device includes isolation circuits disconnecting cell arrays from sense amplifiers, and isolation signal generating circuits generating isolation signals that control the isolation circuits. The isolation signal generating circuits are hierarchically divided into main isolation signal generating circuits and sub isolation signal generating circuits. The sub isolation signal generating circuits generate sub isolation signals having a first potential on a high-potential side. The main isolation signal generating circuits generate main isolation signals having a second potential on the high-potential side, the second potential being lower than the first potential.

Abstract: A mix door D, which is arranged in a limited space defined between an upstream air passage 10 in which an evaporator 3 is installed and a downstream air passage 11 in which a heater core 4 is installed, is of a sliding type. By guiding a door proper 12 by using a cam groove, a seal member 15 bonded to the door proper 12 is pressed against a contacting member 13 only when the door proper 12 assumes its close position. Smoothed operation of the door proper 12 is achieved with a compact construction of a unit, and sealing and temperature controlling performance is increased.

Abstract: To reduce wasteful power consumption at an input circuit without increasing in number of exterior wiring, there are provided command input circuits 24 and 26 for latching a command CMD on the rise of an internal clock CLK1, a command decoder for decoding the latched command, a chip select signal input circuits 41, 40 and 20 for activating an enable signal EN1 in response to activation of a chip select signal *CS, deactivating the EN1 in response to deactivation of the *CS after the next pulse of an external clock CLK and generating an internal chip select signal *CSC by synchronizing the *CS with the CLK, a clock input circuit 21 for passing through the CLK while the EN1 is active, and a D-flip-flop for generating a command data activating signal by synchronizing the internal chip select signal *CSC with the CLK1.

Abstract: A semiconductor memory includes memory cell blocks, a burst-length information generating circuit which generates burst-length information based on a burst length, and a block enable circuit which receives the burst-length information. The block enable circuit selectively enables one of the memory cell blocks when the burst length is equal to or shorter than a predetermined burst length and selectively enables a plurality of memory cell blocks based on the burst length when the burst length is longer than the predetermined burst length. Data are read from the above-mentioned one or plurality of memory cell blocks.

Abstract: A novel semiconductor device having two different power circuits is disclosed. Even if the output of the stage before a voltage conversion circuit declines due to the decline of the level of the power circuits or the voltage drop through a resistor, the voltage conversion circuit performs a normal operation. The semiconductor device comprises a first power circuit for generating a first source voltage, a second power circuit for generating a second source voltage higher than the first source voltage, and a second power level detection circuit for detecting the second source voltage. The first power circuit changes the first source voltage in accordance with the result of detection by the second power level detection circuit.

Abstract: A memory device comprises: a plurality of banks each of which includes an array of memory cells; and at least a first and a second internal power generator, provided for each of the plurality of banks, for generating an internal power source voltage which differs from a voltage supplied by an external power source. If the internal common power source voltage in the memory device is lower than the first voltage when the power is on, the first and the second internal power generators in a plurality of banks are activated so as to rapidly raise the common internal power source voltage. When the common internal power source voltage in the memory device is higher than the first voltage and lower than the second voltage, the second internal power generators in the banks are activated to compensate for a drop in the internal power source voltage, which is caused by current leakage.

Abstract: The present invention relates to an internal voltage generating circuit. The internal voltage generating circuit comprises a reference voltage generating circuit for generating a reference voltage, which does not depend on an external power supply; and a comparator including a first input terminal, to which the reference voltage is supplied, a second input terminal, for comparing the voltages of the first and second input terminals and generating an output voltage according to the difference thereof at the output terminal; and an impedance element, which is selectively inserted between the output terminal and the second input terminal of the comparator according to an operation mode.

Abstract: A semiconductor system includes at least one logic chip and at least one memory chip arranged such that one side of the at least one memory chip faces one side of the at least one logic chip. The semiconductor system further includes first input/output nodes, provided for the at least one logic chip, for data transfer with an adjacent memory chip, second input/output nodes, provided for the at least one memory chip, for data transfer with an adjacent logic chip, and a package housing the at least one logic chip and the at least one memory chip, wherein the first input/output nodes are arranged along the one side of the at least one logic chip, and the second input/output nodes are arranged along the one side of the at least one memory chip.

Abstract: An automobile heating, ventilation, and air conditioning (HVAC) unit comprises a heating, ventilation, and air conditioning case permitting the flow of interior air, an evaporator core disposed in the case for taking heat from the interior air to produce cool air, a heater core disposed in the case downstream of the evaporator core for adding heat to the cool air to produce warm air, an air mix chamber defined in the case for blending the cool air with the warm air, an air mix door disposed between the evaporator core and the heater core for controlling the percentage of the cool air and the warm air being fed into the air mix chamber, depending on the position of the air mix door, and a foot-vent communication passage defined in the case by partitioning the rear end of the air mix chamber by a partition wall extending substantially vertically along the inner wall of the case, so that the foot-vent communication passage communicates with the downstream end of the air mix chamber.

Abstract: The present invention relates to a level interface circuit, which receives a first interface input signal having a level H and a level L, as fixed potentials, and a first reference level which is midway therebetween, and a second interface input signals having a level H, a level L and a second reference level determined in accordance with a power source voltage, and which compares an input signal of one of said first and second interface input with one of said first and second reference level signal and generates an output signal, said level interface circuit further comprising: a first and a second transistors, having a common source connection, for receiving said input signal and said reference level signal at respective gates; a current source transistor connected to said source of said first and said second transistors; a load circuit connected to drains of said first and said second transistors; a voltage control transistor provided between said load circuit and said power voltage source; and a voltage c

Abstract: A semiconductor integrated circuit includes a gate extending in a first direction, a diffusion-layer region corresponding to the gate, and a plurality of backing wiring lines connected to the diffusion-layer region and extending in a first wiring layer in a second direction substantially perpendicular to the first direction. The semiconductor integrated circuit further includes connection wiring lines providing connections between the plurality of backing wiring lines and provided in a second wiring layer.

Abstract: A semiconductor memory device capable of conducting test operations includes a plurality of word drivers which keep word lines in an active state when the word drivers are selected until the word drivers are reset. The semiconductor memory device further includes a control circuit which successively selects more than one of the plurality of word drivers so as to achieve simultaneous activation of word lines corresponding to selected ones of the plurality of word drivers during the test operations.

Abstract: A plurality of word lines are disposed on the surface of a semiconductor substrate in a first direction. Two dummy word lines are disposed outside of the outermost word line among the word lines. MISFETs are disposed in correspondence with the word lines and dummy word lines. MISFETs are regularly disposed in the first direction and in a second direction crossing the first direction. One storage region among the source and drain regions of each MISFET is formed with a storage contact hole. The storage regions are distributed only in an area inside of the outermost dummy word line among the dummy word lines. A capacitor is connected to the storage region at the bottom of each storage contact hole. Different voltages are applied to the dummy word lines and the bit regions disposed outside of the outermost dummy word line. A semiconductor device capable of suppressing a standby current error is provided.

Abstract: According to the present invention, there is provided a semiconductor memory device comprising a memory cell array and a redundant memory cell array in which a defective cell in the memory cell array is substituted by a cell in the redundant memory cell array; further comprising: a PROM circuit in which a redundant address corresponding to the defective cell is recorded; a redundant address data holding circuit that holds the data of the redundant address recorded in the PROM circuit on initialisation; a circuit for deciding on redundancy that compares the data held by the redundant address data holding circuit with an address supplied from outside and makes a decision; and a driver circuit for the memory cell array that is actuated in accordance with the result of this decision by the circuit for deciding on redundancy and a driver circuit for the redundant memory cell array.

Abstract: A semiconductor integrated circuit has a voltage generator, a delay gate array, and a current controller. The voltage generator generates an output voltage in response to voltage control signals. The delay gate array has cascaded delay gates for producing a delay. The current controller controls a current flowing to the delay gate array in response to the output voltage of the voltage generator. Consequently, the voltage control signals control the delay produced by the delay gate array. This circuit is capable of precisely controlling the delay with a small number of elements and a small circuit scale.

Abstract: A semiconductor integrated circuit has first and second delay controllers for receiving an input signal, a plurality of object circuits for receiving an internal signal from the first delay circuit through a real line, and a phase comparator. The phase comparator receives the input signal and a dummy internal signal from the second delay controller through a dummy line, and compares the phases of the received signals with each other. Further, the phase comparator controls delays in the first and second delay controllers according to the comparison result. The length of the real line from the first delay controller to any one of the object circuits is substantially identical, and a load value of the dummy line is substantially equal to that of the real line between the first delay controller and any one of the object circuits. Therefore, each of the object circuits or pads receives a phase-locked control signal without regard to the physical position thereof.

Abstract: Invertors 23 and 24 operating under a low source voltage receive a reset signal Vr and an input signal Va respectively. Outputs of invertors 23 and 24 are connected to gates of a pMOS transistor 3 and an nMOS transistor 54 respectively, which operate under a high source voltage. The pMOS transistor 3 and the nMOS transistor 54 are connected in series, operating under a high source voltage. The pMOS transistor 3 has a threshold voltage which is approximately equal to the low source voltage.

Abstract: A semiconductor integrated circuit has a primary delay controller for receiving an external control signal, at least one intermediate delay controller cascaded to the primary delay controller, and a final delay controller cascaded to the intermediate delay controller. The semiconductor integrated circuit further has a phase comparator and a pulse signal generator. The phase comparator compares a phase of the external control signal with a phase of an output signal of the final delay controller, and controls delays in the primary, intermediate, and final delay controllers in accordance with the comparison result. The pulse signal generator receives the external control signal and an output signal of any one of the primary and intermediate delay controllers, and provides a pulse signal whose pulse width is dependent on a period of the external control signal and a value specific to the received output signal.

Abstract: The present invention relates to a semiconductor memory device having a bit line precharge circuit which precharges bit lines forming a data transfer path coupled to cells. The memory device is further provided with a first control circuit which controls the bit line precharge circuit to precharge the bit lines in response to a bit line precharge request, and a second control circuit which recognizes a command input from outside and makes the bit line precharge request with respect to the first control circuit. The second control circuit accepts a selection of whether or not to request automatic precharge of the bit lines when making an entry to a burst mode even when a burst length is set to a full column, and makes the bit line precharge request with respect to the first control circuit so that the bit lines are precharged after the burst mode ends when an entry to the burst mode requests the automatic precharge.

Abstract: The turn-on time of an output transistor is minimized to suppress the average value of the load current, and the load is electrically charged with an intermediate potential prior to outputting data to suppress the instantaneous value of the load current. The output circuit holds the load in an open state when a predetermined reset signal has a first logic level, and drives the load from a high-potential side power source or a low-potential side power source depending on the logic level of the output data when said predetermined reset signal changes to a second logic level, wherein the timing at which the reset signal changes from the first logic to the second logic is delayed at least until the logic level of the output data has settled.