Patents by Inventor Toshiyuki Isa
Toshiyuki Isa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8518760Abstract: The invention provides a display device and a method for manufacturing thereof by increasing a material efficiently as well as simplifying steps. Also, the invention provides a technique for forming a pattern such as a wiring, that is used for forming a display device, to have a predetermined shape with an excellent controllability. The method for manufacturing a display device includes the steps of: forming a lyophobic region; selectively irradiating laser beam in the lyophobic region to form a lyophilic region; selectively discharging a composition, that contains a conductive material, in the lyophilic region to form a gate electrode layer; forming a gate insulating layer and a semiconductor layer over the gate electrode layer; discharging a composition containing a conductive material over the semiconductor layer to form a source electrode layer and a drain electrode layer; and forming a pixel electrode layer on the source or drain electrode layer.Type: GrantFiled: March 17, 2011Date of Patent: August 27, 2013Assignee: Semiconductor Energy Co., Ltd.Inventors: Shunpei Yamazaki, Osamu Nakamura, Shinji Maekawa, Gen Fujii, Toshiyuki Isa
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Patent number: 8513664Abstract: A thin film transistor includes, as a buffer layer, an amorphous semiconductor layer having nitrogen or an NH group between a gate insulating layer and source and drain regions and at least on the source and drain regions side. As compared to a thin film transistor in which an amorphous semiconductor is included in a channel formation region, on-current of a thin film transistor can be increased. In addition, as compared to a thin film transistor in which a microcrystalline semiconductor is included in a channel formation region, off-current of a thin film transistor can be reduced.Type: GrantFiled: June 24, 2009Date of Patent: August 20, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshiyuki Isa, Yasuhiro Jinbo, Sachiaki Tezuka, Koji Dairiki, Hidekazu Miyairi, Shunpei Yamazaki
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Patent number: 8487436Abstract: To provide a semiconductor device and a display device which can be manufactured through a simplified process and the manufacturing technique. Another object is to provide a technique by which a pattern of wirings or the like which is partially constitutes a semiconductor device or a display device can be formed with a desired shape with controllability.Type: GrantFiled: May 12, 2009Date of Patent: July 16, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshiyuki Isa, Masafumi Morisue, Ikuko Kawamata
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Patent number: 8455753Abstract: It is an object of the present invention to minimize an electrode in a solar cell to minimize the solar cell. The present invention provides a method for manufacturing a solar cell comprising the steps of forming a first electrode layer over a substrate, forming a photoelectric conversion layer over the first electrode layer, forming an organic layer over the photoelectric conversion layer, forming an opening reaching the first electrode layer in the photoelectric conversion layer, and forming a second electrode layer by filling the opening with a conductive paste, wherein the organic layer modifies the surface of the photoelectric conversion layer and a contact angle between the conductive paste and the photoelectric conversion becomes greater. According to the present invention, wettability of a photoelectric conversion layer can be decreased by forming an organic layer on a surface of the photoelectric conversion layer. Thereby an electrode layer and an insulating isolation layer can be thinned.Type: GrantFiled: January 4, 2006Date of Patent: June 4, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuo Nishi, Tomoyuki Aoki, Toshiyuki Isa, Gen Fujii
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Patent number: 8395156Abstract: An object is to provide a display device whose frame can be narrowed and whose display characteristics are excellent. The display device includes a driver circuit and a pixel portion. The driver circuit and the pixel portion are formed using a dual-gate thin film transistor and a single-gate thin film transistor, respectively. In the dual-gate thin film transistor in the display device, a semiconductor layer is formed using a microcrystalline semiconductor region and a pair of amorphous semiconductor regions, and a gate insulating layer and an insulating layer are in contact with the microcrystalline semiconductor region of the semiconductor layer.Type: GrantFiled: November 17, 2010Date of Patent: March 12, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Toshiyuki Isa
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Patent number: 8394685Abstract: The amorphous silicon film is formed over the microcrystalline silicon film, and plasma treatment is performed on the amorphous silicon film in a mixed gas atmosphere of H2 and Ar at a pressure higher than 1000 Pa, so that etching is performed to expose the microcrystalline silicon film. In the etching, the etching rate of the amorphous silicon film and that of the microcrystalline silicon film is large.Type: GrantFiled: November 22, 2011Date of Patent: March 12, 2013Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki KaishaInventors: Toshiyuki Isa, Tomohiro Kimura
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Patent number: 8389993Abstract: A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.Type: GrantFiled: January 31, 2012Date of Patent: March 5, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Kobayashi, Ikuko Kawamata, Koji Dairiki, Shigeki Komori, Toshiyuki Isa, Shunpei Yamazaki
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Patent number: 8383434Abstract: A method for manufacturing a thin film transistor having high electric characteristics with high productivity. In the method for forming a channel region of a dual-gate thin film transistor including a first gate electrode and a second gate electrode which faces the first gate electrode with the channel region provided therebetween, a first microcrystalline semiconductor film is formed under a first condition for forming a microcrystalline semiconductor film in which a space between crystal grains is filled with an amorphous semiconductor, and a second microcrystalline semiconductor film is formed over the first microcrystalline semiconductor film under a second condition for promoting crystal growth.Type: GrantFiled: February 4, 2011Date of Patent: February 26, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Toshiyuki Isa
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Patent number: 8344378Abstract: An object is to provide a thin film transistor with small off current, large on current, and high field-effect mobility. A silicon nitride layer and a silicon oxide layer which is formed by oxidizing the silicon nitride layer are stacked as a gate insulating layer, and crystals grow from an interface of the silicon oxide layer of the gate insulating layer to form a microcrystalline semiconductor layer; thus, an inverted staggered thin film transistor is manufactured. Since crystals grow from the gate insulating layer, the thin film transistor can have a high crystallinity, large on current, and high field-effect mobility. In addition, a buffer layer is provided to reduce off current.Type: GrantFiled: June 22, 2010Date of Patent: January 1, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Miyako Nakajima, Hidekazu Miyairi, Toshiyuki Isa, Erika Kato, Mitsuhiro Ichijo, Kazutaka Kuriki, Tomokazu Yokoi
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Patent number: 8324018Abstract: Conductive layers having knots are adjacently formed with uniform distance therebetween. Droplets of the conductive layers are discharged to stagger centers of the droplets in a length direction of wirings so that the centers of the discharged droplets are not on the same line in a line width direction between the adjacent conductive layers. Since the centers of the droplets are staggered, parts of the conductive layers each having a widest line width (the widest width of knot) are not connected to each other, and the conductive layers can be formed adjacently with a shorter distance therebetween.Type: GrantFiled: December 18, 2009Date of Patent: December 4, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshiyuki Isa, Gen Fujii, Masafumi Morisue, Ikuko Kawamata
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Publication number: 20120229747Abstract: Provided are a liquid crystal display device with horizontal electric field mode, in which a decrease in driving speed can be suppressed by reducing the resistance of a wiring even when the number of pixels is increased, and a manufacturing method thereof. One of a scan wiring and a signal wiring is divided in an intersection portion where the scan wiring and the signal wiring intersect with each other, and the separated wirings are connected with a connection electrode positioned over a thick insulating film. Accordingly, parasitic capacitance at the intersection portion can be reduced, preventing the decrease in the driving speed. The connection electrode is formed at the same time as formation of a pixel electrode and a common electrode using a low-resistance metal, which contributes to the reduction in manufacturing process of the liquid crystal display device.Type: ApplicationFiled: February 29, 2012Publication date: September 13, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hidekazu MIYAIRI, Tetsuji Ishitani, Dajsuke Kobota, Toshiyuki Isa, Kouhei Toyotaka, Susumu Kawashima
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Publication number: 20120156835Abstract: The amorphous silicon film is formed over the microcrystalline silicon film, and plasma treatment is performed on the amorphous silicon film in a mixed gas atmosphere of H2 and Ar at a pressure higher than 1000 Pa, so that etching is performed to expose the microcrystalline silicon film. In the etching, the etching rate of the amorphous silicon film and that of the microcrystalline silicon film is large.Type: ApplicationFiled: November 22, 2011Publication date: June 21, 2012Applicants: SHARP KABUSHIKI KAISHA, SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Toshiyuki ISA, Tomohiro KIMURA
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Publication number: 20120129288Abstract: A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.Type: ApplicationFiled: January 31, 2012Publication date: May 24, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Satoshi KOBAYASHI, Ikuko Kawamata, Koji Dairiki, Shigeki Komori, Toshiyuki Isa, Shunpei Yamazaki
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Patent number: 8138032Abstract: A thin film transistor includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode; a semiconductor layer which includes a plurality of crystalline regions in an amorphous structure and which forms a channel formation region, in contact with the gate insulating layer; a semiconductor layer including an impurity element imparting one conductivity type, which forms source and drain regions; and a buffer layer including an amorphous semiconductor between the semiconductor layer and the semiconductor layer including an impurity element imparting one conductivity type. The crystalline regions have an inverted conical or inverted pyramidal crystal particle which grows approximately radially in a direction in which the semiconductor layer is deposited, from a position away from an interface between the gate insulating layer and the semiconductor layer.Type: GrantFiled: April 14, 2009Date of Patent: March 20, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Koji Dairiki, Yuji Egi, Yasuhiro Jinbo, Toshiyuki Isa
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Publication number: 20120061676Abstract: A highly reliable transistor in which change in electrical characteristics is suppressed is provided. A highly reliable transistor in which change in electrical characteristics is suppressed is manufactured with high productivity. A display device with less image deterioration over time is provided. An inverted staggered thin film transistor which includes, between a gate insulating film and impurity semiconductor films functioning as source and drain regions, a semiconductor stacked body including a microcrystalline semiconductor region and a pair of amorphous semiconductor regions. In the microcrystalline semiconductor region, the nitrogen concentration on the gate insulating film side is low and the nitrogen concentration in a region in contact with the amorphous semiconductor is high. Further, an interface with the amorphous semiconductor has unevenness.Type: ApplicationFiled: September 7, 2011Publication date: March 15, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Yuji EGI, Tetsuhiro TANAKA, Toshiyuki ISA, Hidekazu MIYAIRI, Koji DAIRIKI, Yoichi KUROSAWA, Kunihiko SUZUKI
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Patent number: 8133771Abstract: A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.Type: GrantFiled: July 16, 2010Date of Patent: March 13, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Satoshi Kobayashi, Ikuko Kawamata, Koji Dairiki, Shigeki Komori, Toshiyuki Isa, Shunpei Yamazaki
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Patent number: 8124972Abstract: The thin film transistor includes a gate insulating layer covering a gate electrode, over a substrate having an insulating surface; a semiconductor layer forming a channel formation region, in which a plurality of crystal regions is included in an amorphous structure; an impurity semiconductor layer imparting one conductivity type which forms a source region and a drain region; and a buffer layer formed from an amorphous semiconductor, which is located between the semiconductor layer and the impurity semiconductor layer. The thin film transistor includes the crystal region which includes minute crystal grains and inverted conical or inverted pyramidal grain each of which grows approximately radially from a position away from an interface between the gate insulating layer and the semiconductor layer toward a direction in which the semiconductor layer is deposited in a region which does not reach the impurity semiconductor layer.Type: GrantFiled: April 24, 2009Date of Patent: February 28, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Koji Dairiki, Hidekazu Miyairi, Toshiyuki Isa, Akiharu Miyanaga, Takuya Hirohashi, Shunpei Yamazaki, Takeyoshi Watabe
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Patent number: 8119468Abstract: Disclosed is a thin film transistor which includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode; a semiconductor layer which functions as a channel formation region; and a semiconductor layer including an impurity element imparting one conductivity type. The semiconductor layer exists in a state that a plurality of crystalline particles is dispersed in an amorphous silicon and that the crystalline particles have an inverted conical or inverted pyramidal shape. The crystalline particles grow approximately radially in a direction in which the semiconductor layer is deposited. Vertexes of the inverted conical or inverted pyramidal crystal particles are located apart from an interface between the gate insulating layer and the semiconductor layer.Type: GrantFiled: April 14, 2009Date of Patent: February 21, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Koji Dairiki, Yuji Egi, Yasuhiro Jinbo, Toshiyuki Isa
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Patent number: 8120030Abstract: Off current of a bottom gate thin film transistor in which a semiconductor layer is shielded from light by a gate electrode is reduced. A thin film transistor includes a gate electrode layer; a first semiconductor layer; a second semiconductor layer, provided on and in contact with the first semiconductor layer; a gate insulating layer between and in contact with the gate electrode layer and the first semiconductor layer; impurity semiconductor layers in contact with the second semiconductor layer; and source and drain electrode layers partially in contact with the impurity semiconductor layers and the first and second semiconductor layers. The entire surface of the first semiconductor layer on the gate electrode layer side is covered by the gate electrode layer; and a potential barrier at a portion where the first semiconductor layer is in contact with the source or drain electrode layer is 0.5 eV or more.Type: GrantFiled: December 8, 2009Date of Patent: February 21, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hiromichi Godo, Satoshi Kobayashi, Hidekazu Miyairi, Toshiyuki Isa, Shunpei Yamazaki
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Publication number: 20120033156Abstract: A liquid crystal display device which includes a pair of substrates, a pixel including a liquid crystal element between the pair of substrates, a lighting portion provided on the outer side of the pair of substrates, a first polarizing member between the pair of substrates and the lighting portion, a reflective member provided outside the lightning portion, a second polarizing member on a side opposite to the first polarizing member with the pair of substrates provided therebetween, and a first optical sensor and a second optical sensor. The first optical sensor has a function of detecting illuminance of external light, and the second optical sensor has a function of detecting a color tone of polarized light emitted from the pixel portion. The lightning portion can emits light having a predetermined wavelength depending on the color tone of the pixel portion which is detected by the second optical sensor.Type: ApplicationFiled: August 4, 2011Publication date: February 9, 2012Inventors: Shunpei YAMAZAKI, Satoshi TORIUMI, Toshiyuki ISA