Patents by Inventor Toshiyuki Isa
Toshiyuki Isa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090321743Abstract: A thin film transistor includes, as a buffer layer, an amorphous semiconductor layer having nitrogen or an NH group between a gate insulating layer and source and drain regions and at least on the source and drain regions side. As compared to a thin film transistor in which an amorphous semiconductor is included in a channel formation region, on-current of a thin film transistor can be increased. In addition, as compared to a thin film transistor in which a microcrystalline semiconductor is included in a channel formation region, off-current of a thin film transistor can be reduced.Type: ApplicationFiled: June 24, 2009Publication date: December 31, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Toshiyuki ISA, Yasuhiro JINBO, Sachiaki TEZUKA, Koji DAIRIKI, Hidekazu MIYAIRI, Shunpei YAMAZAKI
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Publication number: 20090321737Abstract: A thin film transistor includes, as a buffer layer, a semiconductor layer which contains nitrogen and includes crystal regions in an amorphous structure between a gate insulating layer and source and drain regions, at least on the source and drain regions side. As compared to a thin film transistor in which an amorphous semiconductor is included in a channel formation region, on-current of a thin film transistor can be increased. In addition, as compared to a thin film transistor in which a microcrystalline semiconductor is included in a channel formation region, off-current of a thin film transistor can be reduced.Type: ApplicationFiled: June 24, 2009Publication date: December 31, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Toshiyuki ISA, Yasuhiro JINBO, Sachiaki TEZUKA, Koji DAIRIKI, Hidekazu MIYAIRI, Shunpei YAMAZAKI, Takuya HIROHASHI
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Patent number: 7635889Abstract: Conductive layers having knots are adjacently formed with uniform distance therebetween. Droplets of the conductive layers are discharged to stagger centers of the droplets in a length direction of wirings so that the centers of the discharged droplets are not on the same line in a line width direction between the adjacent conductive layers. Since the centers of the droplets are staggered, parts of the conductive layers each having a widest line width (the widest width of knot) are not connected to each other, and the conductive layers can be formed adjacently with a shorter distance therebetween.Type: GrantFiled: January 17, 2006Date of Patent: December 22, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshiyuki Isa, Gen Fujii, Masafumi Morisue, Ikuko Kawamata
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Publication number: 20090267068Abstract: The thin film transistor includes a gate insulating layer covering a gate electrode, over a substrate having an insulating surface; a semiconductor layer forming a channel formation region, in which a plurality of crystal regions is included in an amorphous structure; an impurity semiconductor layer imparting one conductivity type which forms a source region and a drain region; and a buffer layer formed from an amorphous semiconductor, which is located between the semiconductor layer and the impurity semiconductor layer. The thin film transistor includes the crystal region which includes minute crystal grains and inverted conical or inverted pyramidal grain each of which grows approximately radially from a position away from an interface between the gate insulating layer and the semiconductor layer toward a direction in which the semiconductor layer is deposited in a region which does not reach the impurity semiconductor layer.Type: ApplicationFiled: April 24, 2009Publication date: October 29, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Koji DAIRIKI, Hidekazu MIYAIRI, Toshiyuki ISA, Akiharu MIYANAGA, Takuya HIROHASHI, Shunpei YAMAZAKI, Takeyoshi WATABE
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Patent number: 7608531Abstract: To provide a semiconductor device and a display device which can be manufactured through a simplified process and the manufacturing technique. Another object is to provide a technique by which a pattern of wirings or the like which is partially constitutes a semiconductor device or a display device can be formed with a desired shape with controllability.Type: GrantFiled: January 17, 2006Date of Patent: October 27, 2009Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toshiyuki Isa, Masafumi Morisue, Ikuko Kawamata
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Publication number: 20090261328Abstract: Disclosed is a thin film transistor which includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode; a semiconductor layer which functions as a channel formation region; and a semiconductor layer including an impurity element imparting one conductivity type. The semiconductor layer exists in a state that a plurality of crystalline particles is dispersed in an amorphous silicon and that the crystalline particles have an inverted conical or inverted pyramidal shape. The crystalline particles grow approximately radially in a direction in which the semiconductor layer is deposited. Vertexes of the inverted conical or inverted pyramidal crystal particles are located apart from an interface between the gate insulating layer and the semiconductor layer.Type: ApplicationFiled: April 14, 2009Publication date: October 22, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hidekazu MIYAIRI, Koji DAIRIKI, Yuji EGI, Yasuhiro JINBO, Toshiyuki ISA
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Publication number: 20090224237Abstract: To provide a semiconductor device and a display device which can be manufactured through a simplified process and the manufacturing technique. Another object is to provide a technique by which a pattern of wirings or the like which is partially constitutes a semiconductor device or a display device can be formed with a desired shape with controllability.Type: ApplicationFiled: May 12, 2009Publication date: September 10, 2009Inventors: Toshiyuki Isa, Masafumi Morisue, Ikuko Kawamata
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Publication number: 20090224249Abstract: A manufacture process of a thin film transistor mounted on an EL display device is simplified. A thin film transistor is manufactured by stacking a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film; forming a first resist mask over the stacked films; performing first etching to form a thin-film stack body; performing second etching by side etching is conducted on the thin-film stack body to form a gate electrode layer; and forming a source and drain electrode layer and the like with use of a second resist mask. An EL display device is manufactured using the thin film transistor.Type: ApplicationFiled: February 20, 2009Publication date: September 10, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hidekazu Miyairi, Shigeki Komori, Toshiyuki Isa, Atsushi Umezaki
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Publication number: 20090152559Abstract: A manufacturing method of a thin film transistor and a display device using a small number of masks is provided. A first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked. Then, a resist mask having a recessed portion is formed thereover using a multi-tone mask. First etching is performed to form a thin-film stack body, and second etching in which the thin-film stack body is side-etched is performed to form a gate electrode layer. The resist is made to recede, and then, a source electrode, a drain electrode, and the like are formed; accordingly, a thin film transistor is manufactured.Type: ApplicationFiled: December 2, 2008Publication date: June 18, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hidekazu Miyairi, Shigeki Komori, Toshiyuki Isa, Ryu Komatsu
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Publication number: 20090057672Abstract: A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.Type: ApplicationFiled: August 22, 2008Publication date: March 5, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Satoshi KOBAYASHI, Ikuko KAWAMATA, Koji DAIRIKI, Shigeki KOMORI, Toshiyuki ISA, Shunpei YAMAZAKI
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Publication number: 20090061721Abstract: A method for manufacturing a semiconductor device having flexibility by separating an element that is manufactured by a comparatively low-temperature (temperature of less than 500° C.) process from a substrate is provided. The element is separated from a glass substrate by the following steps: forming a silicone layer over a glass substrate; performing plasma treatment to the surface of the silicone layer to weaken the surface of the silicone layer; stacking an organic compound layer over the silicone layer; and forming an element that is manufactured through a process at a comparatively low-temperature, typically, a temperature that the organic compound can withstand, over the compound layer.Type: ApplicationFiled: August 25, 2008Publication date: March 5, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Toshiyuki ISA
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Publication number: 20090004772Abstract: An object of the invention is to provide a method for manufacturing semiconductor devices that are flexible in which elements fabricated using a comparatively low-temperature (less than 500° C.) process are separated from a substrate. After a molybdenum film is formed over a glass substrate, a molybdenum oxide film is formed over the molybdenum film, a nonmetal inorganic film and an organic compound film are stacked over the molybdenum oxide film, and elements fabricated by a comparatively low-temperature (less than 500° C.) process are formed using existing manufacturing equipment for large glass substrates, the elements are separated from the glass substrate.Type: ApplicationFiled: January 24, 2008Publication date: January 1, 2009Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Yasuhiro JINBO, Toshiyuki ISA, Tatsuya HONDA
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Patent number: 7416977Abstract: An object of the present invention is to provide a method for manufacturing a display device with few steps and high yield. One feature of the invention is to form a first mask pattern having low wettability over a conductive layer, form a second mask pattern having high wettability over the conductive layer using the first mask pattern as a mask, and form a mask pattern for etching the conductive layer by removing the first mask pattern. Another feature is to form a pixel electrode by etching the conductive layer.Type: GrantFiled: April 20, 2005Date of Patent: August 26, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kunihiko Fukuchi, Toshiyuki Isa, Gen Fujii
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Publication number: 20080012076Abstract: The invention provides a display device and a method for manufacturing thereof by increasing a material efficiently as well as simplifying steps. Also, the invention provides a technique for forming a pattern such as a wiring, that is used for forming a display device, to have a predetermined shape with an excellent controllability. The method for manufacturing a display device includes the steps of: forming a lyophobic region; selectively irradiating laser beam in the lyophobic region to form a lyophilic region; selectively discharging a composition, that contains a conductive material, in the lyophilic region to form a gate electrode layer; forming a gate insulating layer and a semiconductor layer over the gate electrode layer; discharging a composition containing a conductive material over the semiconductor layer to form a source electrode layer and a drain electrode layer; and forming a pixel electrode layer on the source or drain electrode layer.Type: ApplicationFiled: September 19, 2007Publication date: January 17, 2008Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Osamu NAKAMURA, Shinji MAEKAWA, Gen FUJII, Toshiyuki ISA
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Patent number: 7273773Abstract: The invention provides a display device and a method for manufacturing thereof by increasing a material efficiently as well as simplifying steps. Also, the invention provides a technique for forming a pattern such as a wiring, that is used for forming a display device, to have a predetermined shape with an excellent controllability. The method for manufacturing a display device includes the steps of: forming a lyophobic region; selectively irradiating laser beam in the lyophobic region to form a lyophilic region; selectively discharging a composition, that contains a conductive material, in the lyophilic region to form a gate electrode layer; forming a gate insulating layer and a semiconductor layer over the gate electrode layer; discharging a composition containing a conductive material over the semiconductor layer to form a source electrode layer and a drain electrode layer; and forming a pixel electrode layer on the source or drain electrode layer.Type: GrantFiled: January 26, 2005Date of Patent: September 25, 2007Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Osamu Nakamura, Shinji Maekawa, Gen Fujii, Toshiyuki Isa
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Publication number: 20070085938Abstract: An object of the present invention is to provide a display device which can be manufactured with usability of a material improved and with a manufacturing step simplified and to provide a manufacturing technique thereof. One feature of a display device of the present invention is to comprise an insulating layer having an opening, a first conductive layer formed in the opening, and a second conductive layer formed over the insulating layer and the first conductive layer, wherein the first conductive layer is wider and thicker than the second conductive layer, and the second conductive layer is formed by spraying a droplet including a conductive material.Type: ApplicationFiled: November 29, 2004Publication date: April 19, 2007Applicant: SEMICONDUCTORY ENERGY LABORATORY CO., LTD.Inventors: Shunpei Yamazaki, Hideaki Kuwabara, Shinji Maekawa, Gen Fujii, Toshiyuki Isa
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Publication number: 20060169973Abstract: To provide a semiconductor device and a display device which can be manufactured through a simplified process and the manufacturing technique. Another object is to provide a technique by which a pattern of wirings or the like which is partially constitutes a semiconductor device or a display device can be formed with a desired shape with controllability.Type: ApplicationFiled: January 17, 2006Publication date: August 3, 2006Inventors: Toshiyuki Isa, Masafumi Morisue, Ikuko Kawamata
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Publication number: 20060170111Abstract: Conductive layers having knots are adjacently formed with uniform distance therebetween. Droplets of the conductive layers are discharged to stagger centers of the droplets in a length direction of wirings so that the centers of the discharged droplets are not on the same line in a line width direction between the adjacent conductive layers. Since the centers of the droplets are staggered, parts of the conductive layers each having a widest line width (the widest width of knot) are not connected to each other, and the conductive layers can be formed adjacently with a shorter distance therebetween.Type: ApplicationFiled: January 17, 2006Publication date: August 3, 2006Inventors: Toshiyuki Isa, Gen Fujii, Masafumi Morisue, Ikuko Kawamata
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Publication number: 20060157105Abstract: It is an object of the present invention to minimize an electrode in a solar cell to minimize the solar cell. The present invention provides a method for manufacturing a solar cell comprising the steps of forming a first electrode layer over a substrate, forming a photoelectric conversion layer over the first electrode layer, forming an organic layer over the photoelectric conversion layer, forming an opening reaching the first electrode layer in the photoelectric conversion layer, and forming a second electrode layer by filling the opening with a conductive paste, wherein the organic layer modifies the surface of the photoelectric conversion layer and a contact angle between the conductive paste and the photoelectric conversion becomes greater. According to the present invention, wettability of a photoelectric conversion layer can be decreased by forming an organic layer on a surface of the photoelectric conversion layer. Thereby an electrode layer and an insulating isolation layer can be thinned.Type: ApplicationFiled: January 4, 2006Publication date: July 20, 2006Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kazuo Nishi, Tomoyuki Aoki, Toshiyuki Isa, Gen Fujii
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Publication number: 20060113671Abstract: In a manufacturing process of a semiconductor device, electroplating and CMP have had a problem of increase in manufacturing costs for forming a wiring. Correspondingly, an opening is formed in a porous insulating film after a mask is formed thereover, and a conductive material containing Ag is dropped into the opening. Further, a first conductive layer is formed by baking the conductive material dropped into the opening by selective irradiation with laser light. Subsequently, a metal film is formed over the entire surface by sputtering, and the mask is removed thereafter to have only the metal film remain over the first conductive layer, thereby forming an embedded wiring layer formed with a stack of the first conductive layer containing Ag and the second conductive layer (metal film).Type: ApplicationFiled: November 22, 2005Publication date: June 1, 2006Inventors: Toshiyuki Isa, Shunpei Yamazaki