Patents by Inventor Toshiyuki Kaya

Toshiyuki Kaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10782886
    Abstract: To provide a semiconductor device which suppresses a delay in processing. The semiconductor device is equipped with a plurality of read units which read data stored across a plurality of banks in a memory having the banks, and an access method managing section which, when one of the read units reads the data, determines a read start bank number being a bank number to start reading according to operation situations of the read units excepting the one read unit, and instructs the determined read start bank number to the one read unit.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: September 22, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Nhat Van Huynh, Seiji Mochizuki, Katsushige Matsubara, Toshiyuki Kaya
  • Publication number: 20200195918
    Abstract: A video encoding device includes a local decode generation unit for generating a reference image based on a result of encoding of a divided image, a compression unit for compressing the reference image to generate a compressed data, a reference image storage determination unit for determining whether to store the compressed data in a memory, and an inter-prediction unit for performing motion vector search for inter-coding based on a reference image stored in the memory. The reference image storage determination unit sets an allowable data amount used for storing the reference image for each determined area of the moving image data, and determines whether or not to store the compressed data obtained by compressing the reference image in the memory based on the allowable data amount. Inter-prediction unit sets the reference image corresponding to the compressed data stored in the memory as the search range of motion vector search.
    Type: Application
    Filed: October 24, 2019
    Publication date: June 18, 2020
    Inventors: Maiki HOSOKAWA, Toshiyuki KAYA, Tetsuya SHIBAYAMA, Seiji MOCHIZUKI, Tomohiro UNE, Kazushi AKIE
  • Patent number: 10638148
    Abstract: A video encoding/decoding system includes a video encoding device, and a video decoding device. The video encoding device includes an encoding circuit for encoding an image including a diagnostic image or a normal image. The video decoding device includes a decoding circuit for decoding the image encoded in the encoding circuit, a check signal generation circuit for generating a check signal of the decoded image, a storage circuit for storing the check signal generated by the check signal generation circuit, and a comparison circuit for comparing the check signal stored in the storage circuit with the check signal generated by the check signal generation circuit. The failure is detected by comparing the check signal including an expected value stored in the storage circuit with the check signal including a comparison value generated by the check signal generation circuit by processing the same image data a plurality of times.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: April 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seiji Mochizuki, Toshiyuki Kaya, Hiroshi Ueda, Tetsuya Shibayama
  • Patent number: 10587888
    Abstract: A video encoding/decoding system includes a video encoding device, and a video decoding device. The video encoding device includes an encoding circuit for encoding an image including a diagnostic image or a normal image. The video decoding device includes a decoding circuit for decoding the image encoded in the encoding circuit, a check signal generation circuit for generating a check signal of the decoded image, a storage circuit for storing the check signal generated by the check signal generation circuit, and a comparison circuit for comparing the check signal stored in the storage circuit with the check signal generated by the check signal generation circuit. The failure is detected by comparing the check signal including an expected value stored in the storage circuit with the check signal including a comparison value generated by the check signal generation circuit by processing the same image data a plurality of times.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: March 10, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seiji Mochizuki, Toshiyuki Kaya, Hiroshi Ueda, Tetsuya Shibayama
  • Publication number: 20200073806
    Abstract: A semiconductor device includes first and second CPUs, first and second SPUs for controlling a snoop operation, a controller supporting ASIL D of a functional safety standard and a memory. The controller sets permission of the snoop operation to the first and second SPUs when a software lock-step is not performed. The controller sets prohibition of the snoop operation to the first and second SPUs when the software lock-step is performed. The first CPU executes a first software for the software lock-step, and writes an execution result in a first area for the memory. The second CPU executes a second software for the software lock-step, and writes an execution result in a second area of the memory. The execution result written in the first area is compared with the execution result written in the second area.
    Type: Application
    Filed: June 19, 2019
    Publication date: March 5, 2020
    Inventors: Yuki HAYAKAWA, Toshiyuki KAYA, Shinichi SHIBAHARA
  • Publication number: 20200005353
    Abstract: The present invention provides a service car in which the effect of advertisement is increased and the convenience for users is increased. The processing executed by the CPU of the moving object as the service car includes the steps of obtaining an advertisement from the server (S505), displaying the advertisement on a monitor outside the moving object (S510), accepting input of each signal output from an external information acquisition device (camera, microphone, sensor) provided in the moving object (S520), obtaining external information representing the periphery of the moving object and storing the information (S530), obtaining the travel information of the moving object (S540), estimating the effect of the advertisement based on the external information and the travel information (S550), determining a reward for the advertisement based on a predetermined reward criterion and the effect (S560), and calculating a usage fee for the moving object based on the determined reward.
    Type: Application
    Filed: June 20, 2019
    Publication date: January 2, 2020
    Inventors: Tetsuya SHIBAYAMA, Seiji MOCHIZUKI, Nhat Van HUYNH, Hiroshi UEDA, Toshiyuki KAYA
  • Patent number: 10497149
    Abstract: An image processing apparatus according to one embodiment determines target resolutions of a plurality of source images based on a first horizontal direction size and a first vertical direction size which are a horizontal direction size and a vertical direction size of a backlight control unit of a first display, and a second horizontal direction size and a second vertical direction size which are a horizontal direction size and a vertical direction size of a backlight control unit of a second display, and converts the resolution of each of a plurality of source images such that the resolution of each of a plurality of source images becomes the target resolution.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: December 3, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryuichi Igarashi, Seiji Mochizuki, Katsushige Matsubara, Toshiyuki Kaya
  • Patent number: 10459646
    Abstract: Disclosed is a semiconductor device capable of performing compression and decompression with increased appropriateness. The semiconductor device includes a computing module and a memory control module. The computing module includes a computing unit and a compression circuit. The computing unit performs arithmetic processing. The compression circuit compresses data indicative of the result of arithmetic processing. The memory control module includes an access circuit and a decompression circuit. The access circuit writes compressed data into a memory and reads written data from the memory. The decompression circuit decompresses data read from the memory and outputs the decompressed data to the computing module.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: October 29, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsushige Matsubara, Seiji Mochizuki, Ryoji Hashimoto, Toshiyuki Kaya, Kimihiko Nakazawa, Takahiro Irita, Tetsuji Tsuda
  • Patent number: 10452587
    Abstract: A plurality of transfer modules (402-0 to 402-M) that transfer data between processing units are provided so as to respectively correspond to a plurality of processing units (401-0 to 401-M). First ring buses (403-0 to 403-M) connect, for each of the processing units (401-0 to 401-M), subunits within a corresponding processing unit and the transfer module corresponding to the processing unit so that they form a ring shape. The plurality of transfer modules (402-0 to 402-M) are connected so that they form a ring shape by a second ring bus (404).
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: October 22, 2019
    Assignee: RENESAS ELECTRONICS COPRORATION
    Inventors: Hiroshi Ueda, Seiji Mochizuki, Toshiyuki Kaya, Kenichi Iwata, Katsushige Matsubara
  • Patent number: 10419753
    Abstract: A display area can be smoothly moved. A semiconductor device sequentially receives a plurality of whole images, each of which includes a plurality of small screen images and which are temporally continuous and form a moving image, and decodes a received whole image. Here, the semiconductor device includes a reception unit that receives the whole image including the small screen images, a determination unit that determines a decoding area which includes a small screen image to be decoded and which is included in the whole image, and a decoding unit that decodes the small screen image in the decoding area which is determined by the determination unit and which is included in the whole image. The determination unit determines a new decoding area when a small screen image of intra frame appears in the decoding area.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: September 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazushi Akie, Seiji Mochizuki, Toshiyuki Kaya, Katsushige Matsubara, Hiroshi Ueda, Ren Imaoka, Ryoji Hashimoto
  • Patent number: 10419663
    Abstract: A semiconductor device includes: an encoding processing unit that stores an encoded stream of an input data that is encoded based on the specified encoding control information; a buffer management unit that calculates the transmission buffer occupancy indicating the amount of data stored in a transmission buffer according to the generated data amount, and the reception buffer occupancy indicating the amount of data stored in a reception buffer, which is the destination of the encoded stream; and a control information specifying unit that, when the transmission buffer occupancy is equal to or less than a first threshold, specifies the encoding control information based on the reception buffer occupancy, and when the transmission buffer occupancy is greater than the first threshold, specifies the encoding control information to further reduce the generated data amount than in the case of equal to or less than the first threshold, to the encoding processing unit.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: September 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Shibayama, Toshiyuki Kaya, Seiji Mochizuki, Ryoji Hashimoto
  • Patent number: 10349072
    Abstract: An in-vehicle system includes a camera having an encoder encoding video obtained by the camera, an image processing apparatus which receives the encoded video from the camera, and an image recognition processing circuit performing image recognition on decoded video data from the image processing apparatus. The image processing apparatus includes a codec processing circuit which decodes the encoded video, a plurality of image processing circuits which execute tasks in parallel, an estimating circuit which estimates estimation time in which a process of the task is completed in each of the image processing circuit on the basis of the number of access times to a bus which is obtained on the basis of a parameter of decoding used in the codec processing circuit, and a scheduling circuit which schedules tasks to be executed by the plurality of image processing circuit on the basis of the estimation time.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: July 9, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsushige Matsubara, Takayuki Matsumi, Seiji Mochizuki, Kenichi Iwata, Toshiyuki Kaya
  • Patent number: 10334262
    Abstract: The present invention is directed to reduce deterioration in parallel processing capability. In a moving-picture decoding processing apparatus, information of a first plurality of frames and a second plurality of frames is supplied from a decoding control unit to first and second decoding processing units. For decoding the information from an intermediate point to an end point of a second preceding frame by the second decoding unit in a third period, use of a result of the process of the first decoding processing unit in the third period is inhibited, and use of a result of the process of a first preceding frame by the first decoding processing unit in a second period is permitted by an end signal.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: June 25, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsushige Matsubara, Seiji Mochizuki, Toshiyuki Kaya, Tetsuya Shibayama
  • Patent number: 10296475
    Abstract: A data processing system includes a plurality of data processing devices that perform in parallel data processing on the basis of initial setup data. The data processing devices each has a unique ID and includes a plurality of registers that store the initial setup data and a transfer circuit. The transfer circuit receives packets including a payload that is the initial setup data, shared information, a destination ID and a destination address and, when the shared information indicates that the payload is the initial setup data to be set commonly into the plurality of the data processing devices including its own data processing device, transfers the payload to the register that the destination address indicates irrespective of mismatching between the destination ID and its own ID.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: May 21, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi Ueda, Ren Imaoka, Seiji Mochizuki, Toshiyuki Kaya
  • Publication number: 20190146683
    Abstract: To provide a semiconductor device which suppresses a delay in processing. The semiconductor device is equipped with a plurality of read units which read data stored across a plurality of banks in a memory having the banks, and an access method managing section which, when one of the read units reads the data, determines a read start bank number being a bank number to start reading according to operation situations of the read units excepting the one read unit, and instructs the determined read start bank number to the one read unit.
    Type: Application
    Filed: September 11, 2018
    Publication date: May 16, 2019
    Inventors: Nhat Van HUYNH, Seiji MOCHIZUKI, Katsushige MATSUBARA, Toshiyuki KAYA
  • Patent number: 10268626
    Abstract: A data processing device includes a data selector circuit that divides a plurality of types of data into another plurality of types of data in accordance with a classification of the data, a plurality of compression circuits that respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data, and a data transmission circuit that transmits the plurality of types of compressed data to a terminal.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 23, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takahiko Sugimoto, Tomohiro Une, Hiroshi Ueda, Ryoji Hashimoto, Toshiyuki Kaya
  • Patent number: 10241706
    Abstract: There is a problem that memory protection against access to a shared memory by a sub-arithmetic unit used by a program executed in a main-arithmetic unit cannot be performed in a related-art semiconductor device. According to one embodiment, a semiconductor device includes a sub-arithmetic unit configured to execute a process of a part of a program executed by a main-arithmetic unit, and a shared memory shared by the main-arithmetic unit and the sub-arithmetic unit, in which the sub-arithmetic unit includes a memory protection unit configured to permit or prohibit access to the shared memory based on an access permission range address value provided from the main-arithmetic unit, the access to the shared memory being access that arises from a process executed by the sub-arithmetic unit.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: March 26, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seiji Mochizuki, Katsushige Matsubara, Ren Imaoka, Hiroshi Ueda, Ryoji Hashimoto, Toshiyuki Kaya
  • Patent number: 10225563
    Abstract: Making effective use of an image encoder and an image decoder for processing a color image of a general-purpose standard bit depth, an image transmission device capable of transmitting/receiving a monochrome image of a higher bit depth is configured. An image transmission device includes an image encoder to encode a high bit-depth monochrome image and output encoded data and an image decoder to generate, by decoding the encoded data received via a transmission path, a high bit-depth monochrome image. The image encoder decomposes the input high bit-depth image data into plural bit planes corresponding to color image data of a standard bit depth and encodes the standard bit-depth color image data. The image decoder decodes the color image data of the standard bit depth and synthesizes, from the decoded standard bit-depth color image data, a high bit-depth monochrome image.
    Type: Grant
    Filed: July 9, 2016
    Date of Patent: March 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tomohiro Une, Takahiko Sugimoto, Kwangsoo Park, Toshiyuki Kaya, Tetsuya Shibayama, Seiji Mochizuki
  • Publication number: 20180343461
    Abstract: A video encoding/decoding system includes a video encoding device, and a video decoding device. The video encoding device includes an encoding circuit for encoding an image including a diagnostic image or a normal image. The video decoding device includes a decoding circuit for decoding the image encoded in the encoding circuit, a check signal generation circuit for generating a check signal of the decoded image, a storage circuit for storing the check signal generated by the check signal generation circuit, and a comparison circuit for comparing the check signal stored in the storage circuit with the check signal generated by the check signal generation circuit. The failure is detected by comparing the check signal including an expected value stored in the storage circuit with the check signal including a comparison value generated by the check signal generation circuit by processing the same image data a plurality of times.
    Type: Application
    Filed: August 2, 2018
    Publication date: November 29, 2018
    Inventors: Seiji MOCHIZUKI, Toshiyuki KAYA, Hiroshi UEDA, Tetsuya SHIBAYAMA
  • Patent number: 10123022
    Abstract: In a picture encoding device and a picture decoding device, the access to a reference frame memory is suppressed. The picture encoding device is comprised of a first encoder for intra picture encoding, a second encoder for inter picture encoding, and an intermediate buffer. A local decoded picture generated by the first encoder is stored as a reference picture in the intermediate buffer, and the inter picture encoding by the second encoder is performed by referring to the local decoded picture in the intermediate buffer. A picture decoding device is comprised of a first decoder for intra picture decoding, a second decoder for inter picture decoding, and an intermediate buffer. A local decoded picture generated by the first decoder is stored as a reference picture in the intermediate buffer, and the inter picture decoding by the second decoder is performed by referring the local decoded picture in the intermediate buffer.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: November 6, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiyuki Kaya, Seiji Mochizuki, Tetsuya Shibayama, Kenichi Iwata, Hiroshi Ueda, Ren Imaoka