Patents by Inventor Toshiyuki Kaya

Toshiyuki Kaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190146683
    Abstract: To provide a semiconductor device which suppresses a delay in processing. The semiconductor device is equipped with a plurality of read units which read data stored across a plurality of banks in a memory having the banks, and an access method managing section which, when one of the read units reads the data, determines a read start bank number being a bank number to start reading according to operation situations of the read units excepting the one read unit, and instructs the determined read start bank number to the one read unit.
    Type: Application
    Filed: September 11, 2018
    Publication date: May 16, 2019
    Inventors: Nhat Van HUYNH, Seiji MOCHIZUKI, Katsushige MATSUBARA, Toshiyuki KAYA
  • Patent number: 10268626
    Abstract: A data processing device includes a data selector circuit that divides a plurality of types of data into another plurality of types of data in accordance with a classification of the data, a plurality of compression circuits that respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data, and a data transmission circuit that transmits the plurality of types of compressed data to a terminal.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 23, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takahiko Sugimoto, Tomohiro Une, Hiroshi Ueda, Ryoji Hashimoto, Toshiyuki Kaya
  • Patent number: 10241706
    Abstract: There is a problem that memory protection against access to a shared memory by a sub-arithmetic unit used by a program executed in a main-arithmetic unit cannot be performed in a related-art semiconductor device. According to one embodiment, a semiconductor device includes a sub-arithmetic unit configured to execute a process of a part of a program executed by a main-arithmetic unit, and a shared memory shared by the main-arithmetic unit and the sub-arithmetic unit, in which the sub-arithmetic unit includes a memory protection unit configured to permit or prohibit access to the shared memory based on an access permission range address value provided from the main-arithmetic unit, the access to the shared memory being access that arises from a process executed by the sub-arithmetic unit.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: March 26, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seiji Mochizuki, Katsushige Matsubara, Ren Imaoka, Hiroshi Ueda, Ryoji Hashimoto, Toshiyuki Kaya
  • Patent number: 10225563
    Abstract: Making effective use of an image encoder and an image decoder for processing a color image of a general-purpose standard bit depth, an image transmission device capable of transmitting/receiving a monochrome image of a higher bit depth is configured. An image transmission device includes an image encoder to encode a high bit-depth monochrome image and output encoded data and an image decoder to generate, by decoding the encoded data received via a transmission path, a high bit-depth monochrome image. The image encoder decomposes the input high bit-depth image data into plural bit planes corresponding to color image data of a standard bit depth and encodes the standard bit-depth color image data. The image decoder decodes the color image data of the standard bit depth and synthesizes, from the decoded standard bit-depth color image data, a high bit-depth monochrome image.
    Type: Grant
    Filed: July 9, 2016
    Date of Patent: March 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tomohiro Une, Takahiko Sugimoto, Kwangsoo Park, Toshiyuki Kaya, Tetsuya Shibayama, Seiji Mochizuki
  • Publication number: 20180343461
    Abstract: A video encoding/decoding system includes a video encoding device, and a video decoding device. The video encoding device includes an encoding circuit for encoding an image including a diagnostic image or a normal image. The video decoding device includes a decoding circuit for decoding the image encoded in the encoding circuit, a check signal generation circuit for generating a check signal of the decoded image, a storage circuit for storing the check signal generated by the check signal generation circuit, and a comparison circuit for comparing the check signal stored in the storage circuit with the check signal generated by the check signal generation circuit. The failure is detected by comparing the check signal including an expected value stored in the storage circuit with the check signal including a comparison value generated by the check signal generation circuit by processing the same image data a plurality of times.
    Type: Application
    Filed: August 2, 2018
    Publication date: November 29, 2018
    Inventors: Seiji MOCHIZUKI, Toshiyuki KAYA, Hiroshi UEDA, Tetsuya SHIBAYAMA
  • Patent number: 10123022
    Abstract: In a picture encoding device and a picture decoding device, the access to a reference frame memory is suppressed. The picture encoding device is comprised of a first encoder for intra picture encoding, a second encoder for inter picture encoding, and an intermediate buffer. A local decoded picture generated by the first encoder is stored as a reference picture in the intermediate buffer, and the inter picture encoding by the second encoder is performed by referring to the local decoded picture in the intermediate buffer. A picture decoding device is comprised of a first decoder for intra picture decoding, a second decoder for inter picture decoding, and an intermediate buffer. A local decoded picture generated by the first decoder is stored as a reference picture in the intermediate buffer, and the inter picture decoding by the second decoder is performed by referring the local decoded picture in the intermediate buffer.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: November 6, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiyuki Kaya, Seiji Mochizuki, Tetsuya Shibayama, Kenichi Iwata, Hiroshi Ueda, Ren Imaoka
  • Publication number: 20180288418
    Abstract: A semiconductor device includes a hash generator, a reference hash list, a frame mode determination unit, and an intra prediction unit. The hash generator generates a hash value of a target frame to be encoded. The reference hash list is to record the hash value generated by the hash generator. The frame mode determination unit compares the hash value generated by the hash generator and the hash value in the reference hash list. The intra prediction unit performs intra prediction for the target frame to be encoded. When the hash value of the target frame to be encoded coincides with any of the hash values in the reference hash list, the intra prediction unit skips an encoding process, and outputs encoded information corresponding to any of the hash values in the reference hash list.
    Type: Application
    Filed: June 6, 2018
    Publication date: October 4, 2018
    Inventors: Ren IMAOKA, Seiji MOCHIZUKI, Toshiyuki KAYA, Kazushi AKIE, Ryoji HASHIMOTO
  • Publication number: 20180276850
    Abstract: An image processing apparatus according to one embodiment determines target resolutions of a plurality of source images based on a first horizontal direction size and a first vertical direction size which are a horizontal direction size and a vertical direction size of a backlight control unit of a first display, and a second horizontal direction size and a second vertical direction size which are a horizontal direction size and a vertical direction size of a backlight control unit of a second display, and converts the resolution of each of a plurality of source images such that the resolution of each of a plurality of source images becomes the target resolution.
    Type: Application
    Filed: January 3, 2018
    Publication date: September 27, 2018
    Inventors: Ryuichi IGARASHI, Seiji MOCHIZUKI, Katsushige MATSUBARA, Toshiyuki KAYA
  • Patent number: 10051280
    Abstract: A video encoding/decoding system includes a video encoding device and a video decoding device. The video encoding device includes an encoding part for encoding a diagnostic image or normal image. The video decoding device includes a decoding part for decoding the image encoded by the encoding part, a check signal generation part for generating a check signal of the decoded image, a storage part for storing the expected value of the check signal of the diagnostic image or the check signal generated by the check signal generation part, and a comparison part for comparing the check signal stored in the storage part with the check signal generated by the check signal generation part, in order to detect failure in all the paths from the image input part of the video encoding device to the image output part of the video decoding device.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: August 14, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seiji Mochizuki, Toshiyuki Kaya, Hiroshi Ueda, Tetsuya Shibayama
  • Patent number: 10026146
    Abstract: An image processing device includes a decoded data memory, a format-converted data memory, a decoder which decodes compressed image data in units of blocks, writes the decoded data in the blocks into the decoded data memory, and receives a notification that writing of the decoded data has been completed, and a progress notifier which is notified of completion of writing of the decoded data by the decoder, and generates and outputs upon completion of the decoding of a block of data or the writing of a block of the decoded data, a progress signal per picture.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: July 17, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiyuki Kaya, Katsushige Matsubara
  • Patent number: 10021397
    Abstract: A semiconductor device includes a hash generator, a reference hash list, a frame mode determination unit, and an intra prediction unit. The hash generator generates a hash value of a target frame to be encoded. The reference hash list is to record the hash value generated by the hash generator. The frame mode determination unit compares the hash value generated by the hash generator and the hash value in the reference hash list. The intra prediction unit performs intra prediction for the target frame to be encoded. When the hash value of the target frame to be encoded coincides with any of the hash values in the reference hash list, the intra prediction unit skips an encoding process, and outputs encoded information corresponding to any of the hash values in the reference hash list.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: July 10, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ren Imaoka, Seiji Mochizuki, Toshiyuki Kaya, Kazushi Akie, Ryoji Hashimoto
  • Publication number: 20180184080
    Abstract: An object of the present invention is to detect a failure of a camera input in a system including a camera or a video transmission path (camera input). An image processor includes a hash derivation circuit having a computing unit that calculates hash values on an input screen and a storage circuit that stores the hash values. The image processor compares the hash values between multiple frames so as to decide whether the screens have changed or stopped. A failure is detected when the screens are stopped.
    Type: Application
    Filed: October 30, 2017
    Publication date: June 28, 2018
    Inventors: Toshiyuki KAYA, Seiji MOCHIZUKI, Katsushige MATSUBARA, Ryoji HASHIMOTO, Ren IMAOKA
  • Publication number: 20180150428
    Abstract: A data processing device includes a data selector circuit that divides a plurality of types of data into another plurality of types of data in accordance with a classification of the data, a plurality of compression circuits that respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data, and a data transmission circuit that transmits the plurality of types of compressed data to a terminal.
    Type: Application
    Filed: January 31, 2018
    Publication date: May 31, 2018
    Inventors: Takahiko SUGIMOTO, Tomohiro UNE, Hiroshi UEDA, Ryoji HASHIMOTO, Toshiyuki KAYA
  • Publication number: 20180139460
    Abstract: In an image processing device, a motion image decoding processing unit extracts a feature amount of a target image to be decoded from an input stream, and changes a read size of a cache fill from an external memory to a cache memory, based on the feature amount. The feature amount represents an intra macro block ratio in, for example, one picture (frames or fields), or a motion vector variation. When the intra macro block ratio is high, the read size of the cache fill is decreased.
    Type: Application
    Filed: January 15, 2018
    Publication date: May 17, 2018
    Inventors: Keisuke MATSUMOTO, Katsushige MATSUBARA, Seiji MOCHIZUKI, Toshiyuki KAYA, Hiroshi UEDA
  • Patent number: 9946678
    Abstract: A data selector circuit divides a group of data including a plurality of types of data into the plurality of types of data. A first compression circuit and a second compression circuit respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data. The first compression circuit compresses data and obtains compressed data. The second compression circuit compresses data and obtains compressed data. The data transmission circuit-transmits the compressed data and the compressed data to a terminal.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: April 17, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takahiko Sugimoto, Tomohiro Une, Hiroshi Ueda, Ryoji Hashimoto, Toshiyuki Kaya
  • Publication number: 20180077413
    Abstract: A display area can be smoothly moved. A semiconductor device sequentially receives a plurality of whole images, each of which includes a plurality of small screen images and which are temporally continuous and form a moving image, and decodes a received whole image. Here, the semiconductor device includes a reception unit that receives the whole image including the small screen images, a determination unit that determines a decoding area which includes a small screen image to be decoded and which is included in the whole image, and a decoding unit that decodes the small screen image in the decoding area which is determined by the determination unit and which is included in the whole image. The determination unit determines a new decoding area when a small screen image of intra frame appears in the decoding area.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 15, 2018
    Inventors: Kazushi AKIE, Seiji MOCHIZUKI, Toshiyuki KAYA, Katsushige MATSUBARA, Hiroshi UEDA, Ren IMAOKA, Ryoji HASHIMOTO
  • Patent number: 9916276
    Abstract: A data selector circuit divides a group of data including a plurality of types of data into the plurality of types of data. A first compression circuit and a second compression circuit respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data. The first compression circuit compresses data and obtains compressed data. The second compression circuit compresses data and obtains compressed data. The data transmission circuit-transmits the compressed data and the compressed data to a terminal.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: March 13, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takahiko Sugimoto, Tomohiro Une, Hiroshi Ueda, Ryoji Hashimoto, Toshiyuki Kaya
  • Patent number: 9906805
    Abstract: In an image processing device, a motion image decoding processing unit extracts a feature amount of a target image to be decoded from an input stream, and changes a read size of a cache fill from an external memory to a cache memory, based on the feature amount. The feature amount represents an intra macro block ratio in, for example, one picture (frames or fields), or a motion vector variation. When the intra macro block ratio is high, the read size of the cache fill is decreased.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: February 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Keisuke Matsumoto, Katsushige Matsubara, Seiji Mochizuki, Toshiyuki Kaya, Hiroshi Ueda
  • Patent number: 9877044
    Abstract: To reduce noise or the like generated at a boundary of tiles introduced in a video coding method. In a motion vector detection unit, a first tile video signal and a second tile video signal included in one picture are supplied to a first detection unit and a second detection unit, and a reference image is supplied from a frame memory to the first detection unit and the second detection unit. The first detection unit performs processing, by inter prediction, on the video signal positioned on or in the vicinity of a tile boundary between a first tile and another tile among many video signals included in the first tile. In this processing, the first detection unit generates a motion vector so as to preferentially refer to the reference image included in another tile different from the first tile among the reference images read out from the frame memory.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: January 23, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Iwata, Seiji Mochizuki, Toshiyuki Kaya, Ryoji Hashimoto
  • Publication number: 20170365033
    Abstract: An image processing device includes a decoded data memory, a format-converted data memory, a decoder which decodes compressed image data in units of blocks, writes the decoded data in the blocks into the decoded data memory, and receives a notification that writing of the decoded data has been completed, and a progress notifier which is notified of completion of writing of the decoded data by the decoder, and generates and outputs upon completion of the decoding of a block of data or the writing of a block of the decoded data, a progress signal per picture.
    Type: Application
    Filed: August 30, 2017
    Publication date: December 21, 2017
    Inventors: Toshiyuki KAYA, Katsushige Matsubara