Abstract: Disclosed herein is a decoding device that decodes demodulated data obtained by demodulating a quadrature modulated signal arising from digital modulation of a carrier and detects synchronization, the decoding device including, a decoder configured to decode first demodulated data that is the demodulated data obtained by demodulating the quadrature modulated signal and is composed of in-phase axis data and quadrature axis data, and decode second demodulated data obtained by interchanging the in-phase axis data and the quadrature axis data of the first demodulated data, and a synchronization detector configured to detect a boundary between predetermined information symbol sequences from first decoded data obtained by decoding the first demodulated data and detect the boundary from second decoded data obtained by decoding the second demodulated data, the synchronization detector selecting and outputting one of the first decoded data and the second decoded data based on a result of the detection of the boundary.

Abstract: Disclosed herein is a decoding apparatus that performs soft-decision decoding on a linear block code, the apparatus including a hard-decision decoder configured to perform hard-decision decoding on a received word using a hard-decision decoding algorithm; and a soft-decision decoder configured to perform, using a soft-decision algorithm, soft-decision decoding merely on a received word for which the hard-decision decoder has failed in the hard-decision decoding.

Abstract: The present invention provides a decoding apparatus for carrying out a decoding process on a ring-R linear code. The decoding apparatus includes coded-word holding means for acquiring a coded word with a code length reduced by omission of some symbols from the coded word and for holding the coded word; known-information addition means for attaching a reliability level of each of the symbols omitted from the coded word to reduce its code length as known symbols each having a known value to the coded word held by the coded-word holding means as known information; and repetitive decoding means for repeatedly carrying out a decoding process using belief propagation on the coded word including the known information attached to the coded word by the known-information addition means.

Abstract: Disclosed is an apparatus for encoding data into linear codes on a ring R, including: as many shift registers as the length of information input thereto, the shift registers having a plurality of memory elements; a shift adding unit for adding values which are cyclically input depending on a check matrix for the linear codes, from the shift registers; a storage unit for storing parity values of the linear codes; and an accumulative adding unit for adding a sum from the shift adding unit and the parity values of the linear codes stored in the storage unit to each other to determine new parity values of the linear codes, and supplying the new parity values to the storage unit.

Abstract: A decoding method for sorting received words in the order of the magnitude of the reliability of the received words, performing belief propagation using a parity check matrix diagonalized in the order to update the reliabilities, and repetitively performing the sorting and the belief propagation for the updated values, includes an inner repeated decoding process step of performing belief propagation using a parity check matrix diagonalized in an order of columns corresponding to symbols having comparatively low reliability values of the received words to update the reliability and repetitively performing the belief propagation based on the updated reliability; the inner repeated decoding process step in the second or later cycle of repetition thereof including diagonalization of the parity check matrix for restricted ones of the columns of the parity check matrix.

Abstract: The present invention relates to a decoding apparatus and method, a program storage medium, and a program, which allow high-performance decoding of a modulation code encoded in accordance with a variable-length table. A 17PP-SISO decoder 181 performs SISO decoding on a signal supplied from a PR-SISO decoder 81 by using a Viterbi decoding algorithm or a BCJR decoding algorithm in accordance with a trellis represented by paths corresponding, in a one-to-one fashion, to overall transitions in an entire encoding process in accordance with an encoding table 201 of a 17PP code. A resultant SISO-decoded signal is supplied to a turbo decoder 84 via a deinterleaver 83. The turbo decoder 84 performs turbo decoding on the signal output from the 17PP-SISO decoder 181. The present invention can be applied to a recording/reproducing apparatus for recording/reproducing a signal on/from a storage medium such as a high-density optical disk.

Abstract: The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P×P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P×P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculations.

Abstract: The present invention is particularly applied to serial concatenated coding and serial concatenated trellis coded modulation. In second encoding 107, which is inner coding, a sequence that is not encoded or that is encoded so as to produce a finite impulse response and a sequence that is encoded so as to produce an infinite impulse response are output. In interleaving 106 before the second encoding 107, the sequences are permuted so as not to be mixed with each other.

Abstract: The present invention can reduce power consumption at the time of tracing.

Abstract: A method and apparatus for recording or reproducing data in which high performance encoding and a high efficiency decoding are realized to lower the decoding error rate. A magnetic recording and/or reproducing apparatus 50 includes, in a recording system, a modulation encoder 52 for modulation encoding input data in a predetermined fashion and an interleaver 53 for interleaving data supplied from the modulation encoder 52 to re-array the data sequence.

Abstract: To appropriately express an erasure position of a code by a small-scale, simple-structured circuit, a soft-output decoding circuit (90) in each element decoder includes a received value and a priori probability information selection circuit (154) to select an input to-be-decoded received value TSR and extrinsic information or interleaved data TEXT, whichever is necessary for soft-output decoding. Based on inner erasure position information IERS supplied from an inner erasure information generating circuit (152), the received value and a priori probability information selection circuit (154) replaces a position where no coded output exists due to puncture or the like with a symbol whose likelihood is “0”. That is, the received value and a priori probability information selection circuit (154) outputs information which assures a probability in which a bit corresponding to a position where there is no coded output is “0” or “1” to be “½”.

Abstract: The present invention provides a decoding apparatus for carrying out a decoding process on a ring-R linear code. The decoding apparatus includes coded-word holding means for acquiring a coded word with a code length reduced by omission of some symbols from the coded word and for holding the coded word; known-information addition means for attaching a reliability level of each of the symbols omitted from the coded word to reduce its code length as known symbols each having a known value to the coded word held by the coded-word holding means as known information; and repetitive decoding means for repeatedly carrying out a decoding process using belief propagation on the coded word including the known information attached to the coded word by the known-information addition means.

Abstract: A decoding apparatus and method is disclosed by which the decoder error occurrence probability is suppressed and a high decoding performance can be achieved. An ABP decoding apparatus diagonalizes a parity check matrix, updates LLR values, decodes the LLR values and then adds a decoded word obtained by the decoding to a decoded word list. The ABP decoding apparatus repeats the decoding procedure as inner repetitive decoding by a predetermined number of times. Further, as the ABP decoding apparatus successively changes initial values for priority ranks of the LLR values, it repeats the inner repetitive decoding as outer repetitive decoding by a predetermined number of times. Then, the ABP decoding apparatus selects an optimum one of the decoded words from within a decoded word list obtained by the repeated inner repetitive decoding. The invention is applied to an error correction system.

Abstract: The present invention relates to a decoding apparatus and method, a program storage medium, and a program, which allow high-performance decoding of a modulation code encoded in accordance with a variable-length table. A 17PP-SISO decoder 181 performs SISO decoding on a signal supplied from a PR-SISO decoder 81 by using a Viterbi decoding algorithm or a BCJR decoding algorithm in accordance with a trellis represented by paths corresponding, in a one-to-one fashion, to overall transitions in an entire encoding process in accordance with an encoding table 201 of a 17PP code. A resultant SISO-decoded signal is supplied to a turbo decoder 84 via a deinterleaver 83. The turbo decoder 84 performs turbo decoding on the signal output from the 17PP-SISO decoder 181. The present invention can be applied to a recording/reproducing apparatus for recording/reproducing a signal on/from a storage medium such as a high-density optical disk.

Abstract: A decoding system and method for providing relatively high likelihood of obtaining at least two paths of getting to each decoding state from at least three paths. The system and method also selects a maximum likelihood path from the two paths, where a log likelihood of getting to a state in the decoder is determined by a soft-input value encoded with a trellis so as to provide at least three paths for getting to the state.

Abstract: A decoder that receives, as input, probability information AMP/CR×yt. This probability information is obtained by dividing a channel value obtained by multiplication of received value yt and a predetermined coefficient AMP by the first additive coefficient CR for regulating the amplitude of the received value yt and the probability information 1/CA×APPt obtained by multiplying the a priori probability information APPt by the reciprocal of the second additive coefficient CA for regulating the amplitude of the a priori probability information APPt to a soft-output decoding circuit. The soft-output decoding circuit, which may be a large scale intergrated circuit, generates log soft-output CI×I?t and/or external information 1/CA×EXt using additive coefficients for regulating the amplitude of arithmetic operations in the inside of the soft-output decoding circuit.

Abstract: Error correction coding and decoding according to a serial concatenated modulation system are carried out under high code rate. A coding apparatus 1 comprises three convolutional coders 10, 30 and 50 for carrying out convolutional operation; two interleavers 20 and 40 for rearranging order of data input; and a multi-value mapping circuit 60 for carrying out mapping of a single point on the basis of a predetermined modulation system. The coding apparatus 1 carries out convolutional operation whose code rate is “?” as coding of extrinsic codes by a convolutional coder 10, and carries out convolutional operation whose code rate is “1” as coding of inner codes by a convolutional coder 50, and a multi-value modulation mapping circuit 60 applies mapping to a transmission symbol of a 8 PSK modulation system to output it as a single code transmission symbol.

Abstract: A decoder for performing log-sum corrections by means of a linear approximation, putting stress on speed, with a reduced circuit dimension without adversely affecting the decoding performance of the circuit. The decoder includes a linear approximation circuit that computes the log-sum corrections using the function F=?a P?Q+b, where the coefficient ?a represents the gradient of the function and the coefficient b represents, the intercept and are expressed by a power exponent of 2.

Abstract: The present invention relates to a decoding method and a decoder, a program, a recording-and-reproducing apparatus and a method, and a reproducing apparatus and a method that are suitable for decoding encoded data encoded by using a linear code on ring R. A low-density processing unit performs parity-check-matrix low-density processing, performs linear combination for rows of a parity check matrix included in an obtained reception word, and generates a parity check matrix according to the linear-combination result, thereby reducing the density of the parity check matrix used for decoding, at step S21. Then, at step S22, an LDPC decoding unit performs decoding by using a sum product algorithm (SPA) by using the parity check matrix whose density is reduced through the processing performed at step S21. Where the processing at step S22 is finished, the LDPC decoding unit finishes decoding for the reception word. The present invention can be used for an error-correction system.

Abstract: The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P×P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P×P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculations.