Abstract: Disclosed is an apparatus for encoding data into linear codes on a ring R, including: as many shift registers as the length of information input thereto, the shift registers having a plurality of memory elements; a shift adding unit for adding values which are cyclically input depending on a check matrix for the linear codes, from the shift registers; a storage unit for storing parity values of the linear codes; and an accumulative adding unit for adding a sum from the shift adding unit and the parity values of the linear codes stored in the storage unit to each other to determine new parity values of the linear codes, and supplying the new parity values to the storage unit.

Abstract: To carry out error correction coding and decoding according to a serially concatenated coded modulation system with a small circuit scale and high performance. A coding apparatus 1 is designed so that an interleaver 20 interleaves order of bits so that all weights are coded by a convolutional coder 30 with respect to data comprising a series of 3 bits supplied from a convolutional coder 10; the convolutional coder 30 makes as small as possible the total value of the hamming distance of input bit between passes to be the minimum Euclidean distance with respect to data of 3 bits supplied from the interleaver 20; and a multi-value modulation mapping circuit 40 causes the hamming distance of input bits in the convolutional coder 30 as the distance between signal point on the I/Q plane is smaller to subject data of 3 bits supplied from the convolutional coder 30 to mapping.

Abstract: The present invention is particularly applied to serial concatenated coding and serial concatenated trellis coded modulation. In second encoding 107, which is inner coding, a sequence that is not encoded or that is encoded so as to produce a finite impulse response and a sequence that is encoded so as to produce an infinite impulse response are output. In interleaving 106 before the second encoding 107, the sequences are permuted so as not to be mixed with each other.

Abstract: A method and apparatus for recording or reproducing data in which high performance encoding and a high efficiency decoding are realized to lower the decoding error rate. A magnetic recording and/or reproducing apparatus 50 includes, in a recording system, a modulation encoder 52 for modulation encoding input data in a predetermined fashion and an interleaver 53 for interleaving data supplied from the modulation encoder 52 to re-array the data sequence.

Abstract: A magnetic recording and/or reproducing apparatus in which the decoding error rate is to be lowered through realization of the high-performance encoding and the high efficiently decoding. To this end, a magnetic recording and/or reproducing apparatus 50 includes, in its recording system, an error correction coder 51 for error correction encoding input data, an interleaver 52 for interleaving data supplied from the error correction coder 51 for re-arraying the data sequence, a modulation encoder 53 for modulation encoding the data from the interleaver 52 in a predetermined fashion and an interleaver 54 for interleaving the data from the modulation encoder 53 for re-arraying the data sequence.

Abstract: A magnetic recording and/or reproducing apparatus which achieves high performance encoding and high efficiency decoding to lower the decoding error rate. A magnetic recording and/or reproducing apparatus 50 includes, in its recording system, an error correction coder 51 for error correction coding input data and an interleaver 52 for scrambling the sequence of data supplied from the error correction coder 51.

Abstract: An encoding device in a data transmission/reception system includes a first convolutional encoder that encodes an outer code, an interleaver that permutes input data, a second convolutional encoder that encodes an inner code, and a muti-level modulation mapping circuit that performs signal-point mapping based on eight-phase shift keying. When the encoding device uses the second convolutional encoder having two or more memories, the first convolutional encoder uses, as the outer code, a code with a minimum output distance greater than the maximum input distance at which the minimum-distance inner code is generated.

Abstract: A register train is provided in addition to a train of memory cells as many as a cut length which are arranged in correspondence to each state. Outputs of selectors at respective stages in the register train corresponding to state 00 are inputted to a register (1021) in the register train and selectors. Outputs of the registers at the front stages are inputted to those three selectors, respectively. The three selectors switch outputs to the post stages in accordance with a control by a control circuit when a reception word is terminated and in the other cases. Thus, when the reception word is terminated, information stored in the register train is transferred as it is. By such an operation, a path which reaches state 00 can be decoded when a reception word is terminated.

Abstract: A magnetic recording and/or reproducing apparatus performing efficient decoding to lower a decoding error rate. A magnetic recording and/or reproducing apparatus 50 includes a modulation SISO decoder 63 for modulation decoding data modulation-encoded in a predetermined fashion by a modulation coder 52. In the magnetic recording and/or reproducing apparatus 50, the modulation SISO decoder 63 is a soft input soft output (SISO) type modulation decoder fed with a soft input signal and issuing a soft output signal. The modulation SISO decoder 63 is fed with a trellis soft output signal D64 supplied from a trellis SISO decoder 62 to find a soft decision value for an error correction coding data D52 fed to the modulation coder 52 of the recording system to generate a modulated soft decision signal D65. The modulation SISO decoder 63 routes the so-generated modulated soft decision signal D65 to a downstream side error correction soft decoder 64.

Abstract: This invention relates to a memory apparatus or the like adaptable to a multi-value recording flash memory and others. A flash memory 10 is designed for 16-value (4-bit) recording. For a write operation, the encoder (12) converts input data Din into an abbreviated Reed-Solomon code to provide write data WD. The converter (13) converts the write data WD into four-bit parallel data. The converted data are fed and written to the each memory cell constituting cell arrays (11) successively. For a read operation, the converter (14) converts read data RD from the cell arrays (11) into one-byte (8-bit) parallel data and supplies the converted data to the decoder (15) for error correction in units of bytes, whereby output data Dout is obtained. Since the Reed-Solomon code is used, sufficient performance with a limited number of errors to be corrected can be obtained.

Abstract: An encoding device in a data transmission/reception system includes a first convolutional encoder that encodes an outer code, an interleaver that permutes input data, a second convolutional encoder that encodes an inner code, and a multi-level modulation mapping circuit that performs signal-point mapping based on eight-phase shift keying. When the encoding device uses the second convolutional encoder having two or more memories, the first convolutional encoder uses, as the outer code with a minimum output distance greater than the maximum input distance at which the minimum-distance inner code is generated.

Abstract: The deterioration of an error characteristic obtained at a point where a transfer method is changed is suppressed. A first adder calculates a SM value obtained when the state 00 is changed to the state 00, and outputs it to a comparator. A second adder calculates a SM value obtained when the state 01 is changed to the state 00, and outputs it to the comparator. The comparator compares the SM values, selects a path having the larger likelihood, and outputs to a register having a set and a reset. An ACS controller detects a condition in which the state transition of fixed information TAB1 is uniquely determined, and outputs a reset signal to the register having a set and a reset, which stores the SM value of that state, to set the value of the register to zero. The ACS controller 85 also outputs set signals to registers having sets and resets, which store the SM values of the states other than the state 00 of the fixed information TAB1, to set them to the maximum value.

Abstract: A path memory and likelihood update circuit 16 provided in a two-step SOVA decoder includes eight RAMs 32a, 32b, . . . , 32h to store path selection information indicative of a selection of a most likely path in each state of an input convolutional code, a trace result memory circuit 34 to store the result of most likely path tracing and output it as delay trace result signal s42, a most likely path &Dgr; memory circuit 35 to select and store a metric difference for the most likely path based on the delay trace result signal s42 and output it as delay most likely &Dgr; signal s43, and a minimum &Dgr; memory circuits 37a and 37b to store a minimum value of the metric difference for the most likely path in each state of the convolutional code based on the delay trace result signal s42 and delay most likely &Dgr; signal s43.

Abstract: Three dual-port RAMs of the number of bits=8 and the number of words=4 are provided in a path memory circuit. Path selection information is sequentially written into the three RAMs every clock in accordance with the control of a control circuit. On the other hand, the path selection information is read out every clock from the RAMs in accordance with the control of the control circuit and is inputted as read path selection information or the like to a tracing circuit. The tracing circuit executes the tracing operation as many as three times on the basis of the read path selection information and trace starting state information which is formed by the control circuit. On the basis of a tracing result, the decoding data and a trace starting state in the subsequent clock are obtained.

Abstract: A register train is provided in addition to a train of memory cells as many as a cut length which are arranged in correspondence to each state. Outputs of selectors at respective stages in the register train corresponding to state 00 are inputted to a register 1021 in the register train and selectors. Outputs of the registers at the front stages are inputted to those three selectors, respectively. The three selectors switch outputs to the post stages in accordance with a control by a control circuit when a reception word is terminated and in the other cases. Thus, when the reception word is terminated, information stored in the register train is transferred as it is. By such an operation, a path which reaches state 00 can be decoded when a reception word is terminated.

Abstract: To decode a code by a small-scale, simple circuit construction, an element decoder (50) includes a to-be-decoded received data selection circuit (70) to select a to-be-decoded received data TSR. The element decoder (50) selects the to-be-decoded received value TSR by the to-be-decoded received value selection circuit (70), based on received value selection information CSR supplied from a control circuit (60), and supplies it to a soft-output decoding circuit (90).

Abstract: A decoder (3′) inputs the probability information AMP/CR×yt obtained by dividing the channel value obtained by multiplication of received value yt and a predetermined coefficient AMP by the first additive coefficient CR for regulating the amplitude of the received value yt and the probability information 1/CA×APPt obtained by multiplying the a priori probability information APPt by the reciprocal of the second additive coefficient CA for regulating the amplitude of the a priori probability information APPt to a soft-output decoding circuit 23 formed on a single semiconductor substrate as a large scale integrated circuit. The soft-output decoding circuit (23) generates log soft-output CI×I&lgr;t and/or external information 1/CA×EXt, using the first additive coefficient CR, the second additive coefficient CA and the third additive coefficient CI for regulating the amplitude of arithmetic operations in the inside of the soft-output decoding circuit (23).

Abstract: To implement plural types of interleaving for decoding each of various codes in an adaptively suitable manner for the code by a simple circuit construction, an interleaver (100) in an element decoder includes a plurality of data storage circuits (407), and in addition, a control circuit (400) which generates address data for use to write data to the storage circuits (407) and address data for use to read date from the storage circuits (400), an address data selection circuit (405) which selects address data to be distributed to the plurality of storage circuits (407) according to a mode indicating the configuration of a code including the type of an interleaving to be done, an input data selection circuit (406) which selects data to be distributed to the plurality of storage circuits (407) according to the mode, and an output data selection circuit (408) which selects data to be outputted according to the mode. Of the plural storage circuits (407), a one to be used is selected.

Abstract: To appropriately express an erasure position of a code by a small-scale, simple-structured circuit, a soft-output decoding circuit (90) in each element decoder includes a received value and a priori probability information selection circuit (154) to select an input to-be-decoded received value TSR and extrinsic information or interleaved data TEXT, whichever is necessary for soft-output decoding. Based on inner erasure position information IERS supplied from an inner erasure information generating circuit (152), the received value and a priori probability information selection circuit (154) replaces a position where no coded output exists due to puncture or the like with a symbol whose likelihood is “0”. That is, the received value and a priori probability information selection circuit (154) outputs information which assures a probability in which a bit corresponding to a position where there is no coded output is “0” or “1” to be “½”.

Abstract: A decoder has a reduced circuit dimension that does not adversely affect the decoding performance of the circuit. The decoder includes an addition/comparison/selection circuit added to give the log likelihood and adapted to compute a correction item expressed in a one-dimensional function relative to a variable and add a predetermined value to the correction term in order to provide a unified symbol for identifying the positiveness or negativeness of the log likelihood for the purpose of computing the log likelihood.