Patents by Inventor Toshiyuki Oishi
Toshiyuki Oishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240085348Abstract: Provided are a measurement device and a measurement method that enable calibration in the event of error variations. A measurement device configured to measure an amount of moisture contained in a medium, the measurement device including: a first probe in which a first cable electrically connectable to a first connection cable is embedded; a second probe in which a second cable electrically connectable to a second connection cable is embedded; and a standard that is fixed at a predetermined positional relationship with the first probe and the second probe even during the measurement, is electrically connectable to the first connection cable and the second connection cable when the measurement is not conducted, and is used for calibration of the measurement.Type: ApplicationFiled: December 16, 2021Publication date: March 14, 2024Applicant: SONY GROUP CORPORATIONInventors: Sachio IIDA, Atsushi YAMADA, Takuya ICHIHARA, Takahiro OISHI, Toshiyuki HIROI
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Patent number: 9570599Abstract: A portion of an AlN spacer layer of a high electron mobility transistor (GaN HEMI) having a nitride semiconductor used therein is removed only in a region directly below a gate electrode and in a vicinity of the region, and a length of a portion where the AlN spacer layer is not present is sufficiently smaller than a distance between a source electrode and a drain electrode.Type: GrantFiled: December 17, 2012Date of Patent: February 14, 2017Assignee: Mitsubishi Electric CorporationInventors: Yutaro Yamaguchi, Toshiyuki Oishi, Hiroshi Otsuka, Koji Yamanaka
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Publication number: 20150249150Abstract: A portion of an AlN spacer layer of a high electron mobility transistor (GaN HEMI) having a nitride semiconductor used therein is removed only in a region directly below a gate electrode and in a vicinity of the region, and a length of a portion where the AlN spacer layer is not present is sufficiently smaller than a distance between a source electrode and a drain electrode.Type: ApplicationFiled: December 17, 2012Publication date: September 3, 2015Applicant: Mitsubishi Electric CorporationInventors: Yutaro YAMAGUCHI, Toshiyuki OISHI, Hiroshi OTSUKA, Koji YAMANAKA
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Patent number: 9111061Abstract: A transistor characteristic calculation apparatus using a large signal equivalent circuit model has a buffer trap circuit provided between a drain terminal and a source terminal such that a parallel circuit including a resistor and a capacitor, a diode, and another parallel circuit including a resistor and a capacitor are in turn connected in series.Type: GrantFiled: December 26, 2012Date of Patent: August 18, 2015Assignee: Mitsubishi Electric CorporationInventors: Hiroshi Otsuka, Toshiyuki Oishi, Yutaro Yamaguchi, Naoki Kosaka, Shinichi Miwa, Koji Yamanaka
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Publication number: 20150035066Abstract: An FET chip is configured to include an oscillation suppression circuit that has a gate capacitance C formed between a gate electrode 5c and two-dimensional electron gas, and a channel resistance R between the gate electrode 5c and a source electrode 7c, and therefore the oscillation suppression circuit is loaded by only an FET process to make an MMIC design unnecessary, so that it is possible to attain stabilization of an FET while suppressing increase in cost, and to suppress oscillation.Type: ApplicationFiled: April 27, 2012Publication date: February 5, 2015Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Hiroshi Otsuka, Toshiyuki Oishi, Eigo Kuwata, Takashi Yamasaki, Makoto Kimura, Masatoshi Nakayama
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Publication number: 20140019096Abstract: A transistor characteristic calculation apparatus using a large signal equivalent circuit model has a buffer trap circuit provided between a drain terminal and a source terminal such that a parallel circuit including a resistor and a capacitor, a diode, and another parallel circuit including a resistor and a capacitor are in turn connected in series.Type: ApplicationFiled: December 26, 2012Publication date: January 16, 2014Inventors: Hiroshi OTSUKA, Toshiyuki OISHI, Yutaro YAMAGUCHI, Naoki KOSAKA, Shinichi MIWA, Koji YAMANAKA
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Patent number: 8624667Abstract: A device includes a source for transmitting an electronic charge through a conduction path; a drain for receiving the electronic charge; a stack for providing at least part of the conduction path; and a gate operatively connected to the stack for controlling a conduction of the electronic charge. The stack includes an insulator layer, an N-polar layer and a barrier layer selected such that, during an operation of the device, the conduction path formed in the N-polar layer includes a two-dimensional electron gas (2DEG) channel and an inversion carrier channel.Type: GrantFiled: August 6, 2012Date of Patent: January 7, 2014Assignee: Mitsubishi Electric Research Laboratories, Inc.Inventors: Koon Hoo Teo, Peijie Feng, Chunjie Duan, Toshiyuki Oishi, Nakayama Masatoshi
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Publication number: 20130175544Abstract: It is an object to attain both high gain and a broad band (that is, to attain both reduction in a gate-drain capacitance and reduction in a source-drain capacitance). Provided is a semiconductor device, including: a GaN channel layer (3) through which electrons travel; a barrier layer (4) which is provided on the GaN channel layer in order to form two-dimensional electron gas in the GaN channel layer and which contains at least any one of In, Al, and Ga and contains N; a gate electrode (8), a source electrode (6), and a drain electrode (7); and a plate (20) formed of a material having polarization, which is provided between the gate electrode (8) and the drain electrode (7), the plate being held in contact with a part of the barrier layer (4).Type: ApplicationFiled: November 10, 2010Publication date: July 11, 2013Applicant: Mitsubishi Electric CorporationInventors: Toshiyuki Oishi, Hiroshi Otsuka, Koji Yamanaka, Kazuhisa Yamauchi, Masatake Hangai, Masatoshi Nakayama
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Publication number: 20130141156Abstract: A device includes a source for transmitting an electronic charge through a conduction path; a drain for receiving the electronic charge; a stack for providing at least part of the conduction path; and a gate operatively connected to the stack for controlling a conduction of the electronic charge. The stack includes an insulator layer, an N-polar layer and a barrier layer selected such that, during an operation of the device, the conduction path formed in the N-polar layer includes a two-dimensional electron gas (2DEG) channel and an inversion carrier channel.Type: ApplicationFiled: August 6, 2012Publication date: June 6, 2013Inventors: Koon Hoo Teo, Peijie Feng, Chunjie Duan, Toshiyuki Oishi, Nakayama Masatoshi
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Publication number: 20130020584Abstract: In the present invention, provided is a semiconductor device, including: a GaN channel layer which is provided on a substrate and through which electrons run; a barrier layer which is provided on the GaN channel layer and which contains at least one of In, Al, and Ga and contains N; a gate electrode which is provided on the barrier layer; and a source electrode and a drain electrode which are provided on the substrate across the gate electrode, in which, in a portion of the barrier layer between the gate electrode and the drain electrode, a magnitude of polarization of the barrier layer is smaller on the gate electrode side than on the drain electrode side. Thus, PAE can be improved by reducing Rd and Cgd simultaneously.Type: ApplicationFiled: April 22, 2010Publication date: January 24, 2013Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Toshiyuki Oishi, Hiroshi Otsuka, Koji Yamanaka, Akira Inoue
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Patent number: 8247844Abstract: An isolation layer for suppressing a leakage current is provided at least between a channel layer and a buffer layer formed under the channel layer in the buffer layer.Type: GrantFiled: October 7, 2009Date of Patent: August 21, 2012Assignee: Mitsubishi Electric CorporationInventors: Toshiyuki Oishi, Yoshitsugu Yamamoto, Hiroshi Otsuka, Koji Yamanaka, Akira Inoue
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Publication number: 20110316047Abstract: The objective of the present invention is to provide a semiconductor device of a hetero-junction field effect transistor that is capable of obtaining a high output and a high breakdown voltage and a manufacturing method of the same. The present invention is a semiconductor device of a hetero junction field effect transistor provided with an AlxGa1-xN channel layer with a composition ratio of Al being x (0<x<1) formed on a substrate, an AlyGa1-yN barrier layer with a composition of Al being y (0<y?1) formed on the channel layer, and source/drain electrodes and a gate electrode formed on the barrier layer, wherein the composition ratio y is larger than the composition ratio x.Type: ApplicationFiled: August 29, 2011Publication date: December 29, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Takuma Nanjo, Muneyoshi Suita, Yuji Abe, Toshiyuki Oishi, Yasunori Tokuda
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Patent number: 8035130Abstract: The objective of the present invention is to provide a semiconductor device of a hetero-junction field effect transistor that is capable of obtaining a high output and a high breakdown voltage and a manufacturing method of the same. The present invention is a semiconductor device of a hetero-junction field effect transistor provided with an AlxGa1-xN channel layer with a composition ratio of Al being x (0<x<1) formed on a substrate, an AlyGa1-yN barrier layer with a composition of Al being y (0<y?1) formed on the channel layer, and source/drain electrodes and a gate electrode formed on the barrier layer, wherein the composition ratio y is larger than the composition ratio x.Type: GrantFiled: March 25, 2008Date of Patent: October 11, 2011Assignee: Mitsubishi Electric CorporationInventors: Takuma Nanjo, Muneyoshi Suita, Yuji Abe, Toshiyuki Oishi, Yasunori Tokuda
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Patent number: 7939943Abstract: A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, which is an antioxidant film for preventing oxidation of the Ta film, and on a p-type contact layer of a nitride semiconductor. On the second Pd film, a pad electrode is formed. The second Pd film as an antioxidant film is formed on the entire upper surface of the Ta film which forms the p electrode, to prevent oxidation of the Ta film. This inhibits the resistance between the p electrode and the pad electrode, thereby preventing a failure in contact between the p electrode and the pad electrode and providing the low-resistance p electrode.Type: GrantFiled: November 11, 2008Date of Patent: May 10, 2011Assignee: Mitsubishi Electric CorporationInventors: Katsuomi Shiozawa, Kyozo Kanamoto, Toshiyuki Oishi, Hiroshi Kurokawa, Kenichi Ohtsuka, Yoichiro Tarui, Yasunori Tokuda
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Patent number: 7842962Abstract: A P-type electrode material is provided on a top surface of a P-type contact layer. The P-type electrode material is formed with an AuGa film, an Au film, a Pt film, and an Au film. The AuGa film is provided on the P-type contact layer. The Au film is provided on the AuGa film. The Pt film is provided on the Au film. The Au film is provided on the Pt film. With this, a nitride semiconductor device having a P-type electrode which can decrease a contact resistance between a P-type contact layer and the P-type electrode is obtained.Type: GrantFiled: November 16, 2005Date of Patent: November 30, 2010Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsuomi Shiozawa, Toshiyuki Oishi, Kazushige Kawasaki, Yuji Abe
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Publication number: 20100244041Abstract: An isolation layer for suppressing a leakage current is provided at least between a channel layer and a buffer layer formed under the channel layer in the buffer layer.Type: ApplicationFiled: October 7, 2009Publication date: September 30, 2010Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Toshiyuki OISHI, Yoshitsugu Yamamoto, Hiroshi Otsuka, Koji Yamanaka, Akira Inoue
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Patent number: 7791097Abstract: A nitride semiconductor device includes an n-type GaN substrate with a semiconductor device formed thereon and an n-type electrode which is a metal electrode formed on the rear surface of the GaN substrate. A surface modified layer and a reaction layer are interposed between the GaN substrate and n-type electrode. The surface modified layer serves as a carrier supplying layer, and is formed by causing the rear surface of the GaN substrate to react with a Si-containing plasma to be modified. The reaction layer is generated by partially removing a deposited material deposited on the surface modified layer by cleaning to generate a deposited layer and then causing Ti contained in a first metal layer and the deposited layer to partially react by heat treatment.Type: GrantFiled: July 2, 2007Date of Patent: September 7, 2010Assignee: Mitsubishi Electric CorporationInventors: Kyozo Kanamoto, Katsuomi Shiozawa, Kazushige Kawasaki, Hitoshi Sakuma, Junichi Horie, Toshihiko Shiga, Toshiyuki Oishi
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Patent number: 7714439Abstract: A nitride semiconductor device according to the present invention includes a P-type contact layer and a P-type electrode provided on the P-type contact layer. The P-type electrode includes a AuGa film provided on the P-type contact layer, a Au film provided on the AuGa film, a Pt film 4 provided on the Au film, and a Au film provided on the Pt film. The ratio of the thickness of the AuGa film to the total thickness of the AuGa film and the Au film is not less than 12% but not more than 46%.Type: GrantFiled: August 24, 2007Date of Patent: May 11, 2010Assignee: Mitsubishi Electric CorporationInventors: Katsuomi Shiozawa, Hitoshi Sakuma, Kazushige Kawasaki, Toshihiko Shiga, Toshiyuki Oishi
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Patent number: 7678597Abstract: A method of manufacturing a semiconductor device provides a semiconductor device with a gallium-nitride-based semiconductor structure that allows long-term stable operation without degradation in device performance. After formation of an insulation film on a surface other than on a ridge surface, an oxygen-containing gas such as O2, O3, NO, N2O, or NO2 is supplied to oxidize a p-type GaN contact layer from the surface and to thereby form an oxide film on the surface of the p-type GaN contact layer. Then, a p-type electrode that establishes contact with the p-type GaN contact layer is formed by evaporation or sputtering on the oxide film and on the insulation film. Heat treatment is subsequently performed at temperatures between 400 and 700° C. in an atmosphere containing a nitrogen-containing gas such as N2 or NH3 or an inert gas such as Ar or He.Type: GrantFiled: November 26, 2008Date of Patent: March 16, 2010Assignee: Mitsubishi Electric CorporationInventors: Kenichi Ohtsuka, Yoichiro Tarui, Yosuke Suzuki, Katsuomi Shiozawa, Kyozo Kanamoto, Toshiyuki Oishi, Yasunori Tokuda, Tatsuo Omori
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Publication number: 20090170304Abstract: A method of manufacturing a semiconductor device is provided, which can reduce the contact resistance of an ohmic electrode to a p-type nitride semiconductor layer and can achieve long-term stable operation. In forming, in an electrode forming step, a p-type ohmic electrode of a metal film by successive lamination of a Pd film which is a first p-type ohmic electrode and a Ta film which is a second p-type ohmic electrode on a p-type GaN contact layer, the metal film is formed to include an oxygen atom. In the presence of an oxygen atom in the metal film, then in a heat-treatment step, the p-type ohmic electrode of the metal film is heat-treated in an atmosphere that contains no oxygen atom-containing gas.Type: ApplicationFiled: December 18, 2008Publication date: July 2, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoichiro Tarui, Kenichi Ohtsuka, Yosuke Suzuki, Katsuomi Shiozawa, Kyozo Kanamoto, Toshiyuki Oishi, Yasunori Tokuda, Tatsuo Omori