Patents by Inventor Toshiyuki Oishi
Toshiyuki Oishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090160054Abstract: A nitride semiconductor device is provided which reduces the contact resistance at the interface between a P-type electrode and a nitride semiconductor layer. A nitride semiconductor device includes a P-type nitride semiconductor layer and a P-type electrode formed on the P-type nitride semiconductor layer. The P-type electrode is formed by successive laminations of a metal layer of a metal having a work function of 5.1 eV or more, a Pd layer of palladium, and a Ta layer of tantalum on the P-type nitride semiconductor layer.Type: ApplicationFiled: November 13, 2008Publication date: June 25, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Katsuomi Shiozawa, Kyozo Kanamoto, Toshiyuki Oishi, Yoichiro Tarui, Yasunori Tokuda
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Publication number: 20090142871Abstract: A method of manufacturing a semiconductor device provides a semiconductor device with a gallium-nitride-based semiconductor structure that allows long-term stable operation without degradation in device performance. After formation of an insulation film on a surface other than on a ridge surface, an oxygen-containing gas such as O2, O3, NO, N2O, or NO2 is supplied to oxidize a p-type GaN contact layer from the surface and to thereby form an oxide film on the surface of the p-type GaN contact layer. Then, a p-type electrode that establishes contact with the p-type GaN contact layer is formed by evaporation or sputtering on the oxide film and on the insulation film. Heat treatment is subsequently performed at temperatures between 400 and 700° C. in an atmosphere containing a nitrogen-containing gas such as N2 or NH3 or an inert gas such as Ar or He.Type: ApplicationFiled: November 26, 2008Publication date: June 4, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kenichi Ohtsuka, Yoichiro Tarui, Yosuke Suzuki, Katsuomi Shiozawa, Kyozo Kanamoto, Toshiyuki Oishi, Yasunori Tokuda, Tatsuo Omori
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Publication number: 20090140389Abstract: A nitride semiconductor device with a p electrode having no resistance between itself and other electrodes, and a method of manufacturing the same are provided. A p electrode is formed of a first Pd film, a Ta film, and a second Pd film, which is an antioxidant film for preventing oxidation of the Ta film, and on a p-type contact layer of a nitride semiconductor. On the second Pd film, a pad electrode is formed. The second Pd film as an antioxidant film is formed on the entire upper surface of the Ta film which forms the p electrode, to prevent oxidation of the Ta film. This inhibits the resistance between the p electrode and the pad electrode, thereby preventing a failure in contact between the p electrode and the pad electrode and providing the low-resistance p electrode.Type: ApplicationFiled: November 11, 2008Publication date: June 4, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Katsuomi Shiozawa, Kyozo Kanamoto, Toshiyuki Oishi, Hiroshi Kurokawa, Kenichi Ohtsuka, Yoichiro Tarui, Yasunori Tokuda
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Publication number: 20090127661Abstract: Semiconductor devices, in particular nitride semiconductor devices for use in the manufacture of laser diodes, prevent peeling-off of the electrode, and at the same time reduces the complexity of processes and a reduction in yield. A nitride semiconductor device according to the invention includes a P-type nitride semiconductor layer with a ridge on its surface, an SiO2 film covering at least the side face of the ridge, an adherence layer formed on a surface of the SiO2 film and composed mainly of silicon, and a P-type electrode formed on the upper surface of the ridge and on a surface of the adherence layer.Type: ApplicationFiled: November 17, 2008Publication date: May 21, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Katsuomi Shiozawa, Kyozo Kanamoto, Toshiyuki Oishi, Hiroshi Kurokawa, Kazushige Kawasaki, Shinji Abe, Hitoshi Sakuma
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Publication number: 20080237639Abstract: The objective of the present invention is to provide a semiconductor device of a hetero-junction field effect transistor that is capable of obtaining a high output and a high breakdown voltage and a manufacturing method of the same. The present invention is a semiconductor device of a hetero-junction field effect transistor provided with an AlxGa1-xN channel layer with a composition ratio of Al being x (0<x<1) formed on a substrate, an AlyGa1-yN barrier layer with a composition of Al being y (0<y?1) formed on the channel layer, and source/drain electrodes and a gate electrode formed on the barrier layer, wherein the composition ratio y is larger than the composition ratio x.Type: ApplicationFiled: March 25, 2008Publication date: October 2, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Takuma NANJO, Muneyoshi Suita, Yuji Abe, Toshiyuki Oishi, Yasunori Tokuda
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Patent number: 7378351Abstract: A nitride semiconductor device is manufactured by the step of forming a nitride semiconductor layer form on a GaN substrate main surface, the step of polishing a back surface of the GaN substrate formed with the above-mentioned nitride semiconductor layer, the step of dry etching the back surface of the GaN substrate subjected to the above-mentioned polishing by using a gas mixture of chlorine and oxygen, and the step of forming an n-type electrode on the back surface of the GaN substrate subjected to the above-mentioned dry etching.Type: GrantFiled: June 3, 2005Date of Patent: May 27, 2008Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsuomi Shiozawa, Toshiyuki Oishi, Kazushige Kawasaki, Zempei Kawazu, Yuji Abe
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Publication number: 20080116575Abstract: A nitride semiconductor device according to the present invention includes a P-type contact layer and a P-type electrode provided on the P-type contact layer. The P-type electrode includes a AuGa film provided on the P-type contact layer, a Au film provided on the AuGa film, a Pt film 4 provided on the Au film, and a Au film provided on the Pt film. The ratio of the thickness of the AuGa film to the total thickness of the AuGa film and the Au film is not less than 12% but not more than 46%.Type: ApplicationFiled: August 24, 2007Publication date: May 22, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Katsuomi Shiozawa, Hitoshi Sakuma, Kazushige Kawasaki, Toshihiko Shiga, Toshiyuki Oishi
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Publication number: 20080023799Abstract: A nitride semiconductor device includes an n-type GaN substrate with a semiconductor device formed thereon and an n-type electrode which is a metal electrode formed on the rear surface of the GaN substrate. A surface modified layer and a reaction layer are interposed between the GaN substrate and n-type electrode. The surface modified layer serves as a carrier supplying layer, and is formed by causing the rear surface of the GaN substrate to react with a Si-containing plasma to be modified. The reaction layer is generated by partially removing a deposited material deposited on the surface modified layer by cleaning to generate a deposited layer and then causing Ti contained in a first metal layer and the deposited layer to partially react by heat treatment.Type: ApplicationFiled: July 2, 2007Publication date: January 31, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kyozo KANAMOTO, Katsuomi Shiozawa, Kazushige Kawasaki, Hitoshi Sakuma, Junichi Horie, Toshihiko Shiga, Toshiyuki Oishi
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Publication number: 20060108596Abstract: A P-type electrode material is provided on a top surface of a P-type contact layer. The P-type electrode material is formed with an AuGa film, an Au film, a Pt film, and an Au film. The AuGa film is provided on the P-type contact layer. The Au film is provided on the AuGa film. The Pt film is provided on the Au film. The Au film is provided on the Pt film. With this, a nitride semiconductor device having a P-type electrode which can decrease a contact resistance between a P-type contact layer and the P-type electrode is obtained.Type: ApplicationFiled: November 16, 2005Publication date: May 25, 2006Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Katsuomi Shiozawa, Toshiyuki Oishi, Kazushige Kawasaki, Yuji Abe
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Publication number: 20060003490Abstract: A nitride semiconductor device is manufactured by the step of forming a nitride semiconductor layer form on a GaN substrate main surface, the step of polishing a back surface of the GaN substrate formed with the above-mentioned nitride semiconductor layer, the step of dry etching the back surface of the GaN substrate subjected to the above-mentioned polishing by using a gas mixture of chlorine and oxygen, and the step of forming an n-type electrode on the back surface of the GaN substrate subjected to the above-mentioned dry etching.Type: ApplicationFiled: June 3, 2005Publication date: January 5, 2006Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Katsuomi Shiozawa, Toshiyuki Oishi, Kazushige Kawasaki, Zempei Kawazu, Yuji Abe
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Patent number: 6635938Abstract: A polysilicon nitride film is formed to cover a polysilicon gate. By heat treatment of the silicon nitride film in an oxygen atmosphere, a silicon oxinitride film is formed. By anisotropically etching the silicon oxinitride film and the silicon nitride film, a sidewall insulating film is formed. By epitaxial growth, selective silicon films of a prescribed film thickness are formed on source and drain regions. During this period, silicon islands are not deposited on the surface of sidewall insulating film. Consequently, a semiconductor device including a transistor of a superior electrical insulation can be obtained.Type: GrantFiled: November 21, 2000Date of Patent: October 21, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takumi Nakahata, Shigemitsu Maruno, Taisuke Furukawa, Naruhisa Miura, Toshiyuki Oishi, Yasunori Tokuda
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Patent number: 6633070Abstract: A field-effect transistor including a gate electrode, silicon layers, and source and drain regions at a surface of a silicon substrate. Sidewall insulating films on the opposite side surfaces of the gate electrode are located between the gate electrode and the silicon layers and contain respective voids.Type: GrantFiled: September 18, 2001Date of Patent: October 14, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Naruhisa Miura, Toshiyuki Oishi, Yuji Abe, Kohei Sugihara
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Patent number: 6624034Abstract: A method of producing a semiconductor device includes forming a gate electrode on a channel region on a surface of a semiconductor region of a semiconductor substrate, the channel region having a depth in the semiconductor substrate; forming a first pair of side wall spacers on opposite sides of the gate electrode; forming elevated semiconductor layers, each elevated semiconductor layer being elevated relative to the channel region, on regions outside of the pair of side wall spacers and in which source and drain regions of a first conductivity type are to be formed; removing the pair of first side wall spacers; and forming a pair of pocket injection regions of a second conductivity type by introducing, after the side wall spacers are removed, a dopant impurity producing the second conductivity type deeper in the semiconductor substrate than a region where the side wall spacers were formed, the pair of pocket injection regions respectively covering only a neighborhood of respective side surface parts of the cType: GrantFiled: June 19, 2002Date of Patent: September 23, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yuji Abe, Naruhisa Miura, Kohei Sugihara, Toshiyuki Oishi, Yasunori Tokuda
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Patent number: 6617654Abstract: Source and drain regions include regions of an epitaxial silicon film on the surface of the substrate and regions in the substrate. The depth of junctions of the source and drain regions is identical to or shallower than the depth of junctions of extension regions. As a result, even if the thickness of the side wall layer is reduced, since the depletion layer of the extension regions with lower impurity concentration compared with the source and drain regions is predominant, the short channel effect has a smaller effect.Type: GrantFiled: September 19, 2001Date of Patent: September 9, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshiyuki Oishi, Kohei Sugihara, Naruhisa Miura, Yuji Abe, Yasunori Tokuda
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Patent number: 6600195Abstract: A semiconductor device capable of preventing variations in threshold voltage and having high reliability is provided. The semiconductor device includes a semiconductor substrate having a semiconductor region, and a field-effect transistor. The field-effect transistor includes a gate electrode, source and drain regions, and a channel region. The channel region includes a pair of lightly doped impurity regions having a relatively low impurity concentration as well as a heavily doped impurity region located between the lightly doped impurity regions and having a relatively high impurity concentration.Type: GrantFiled: August 15, 2000Date of Patent: July 29, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yukio Nishida, Hirokazu Sayama, Hidekazu Oda, Toshiyuki Oishi
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Patent number: 6566734Abstract: In making a field effect transistor, a dummy gate electrode is formed before a gate electrode is formed. Extension regions, a side wall silicon nitride film, source/drain regions, a silicon oxide film, and other elements are formed with respect to the dummy gate electrode. The dummy gate electrode is removed, and a part of the extension regions diffused into a region immediately under the dummy gate electrode is removed. The removed part is filled with silicon selection epitaxial film. Thereafter, the intended gate electrode is formed. This production method produces a field effect transistor that prevents deterioration of electrical characteristics caused by the short channel effect and parasitic resistance.Type: GrantFiled: March 16, 2001Date of Patent: May 20, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kohei Sugihara, Toshiyuki Oishi, Naruhisa Miura, Yuji Abe, Yasunori Tokuda
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Patent number: 6518635Abstract: A major object of the present invention is to provide an improved semiconductor device so as to be able to reduce gate electric field concentration at a channel edge, suppress decrease in the threshold during MOSFET operation and reduce the leakage current. A gate insulation film is formed on a semiconductor substrate. A gate electrode is formed on the semiconductor substrate with the gate insulation film therebetween. The dielectric constant of the gate insulation film is not uniform in the surface.Type: GrantFiled: July 6, 2000Date of Patent: February 11, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsuomi Shiozawa, Toshiyuki Oishi, Yuji Abe, Yasunori Tokuda
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Patent number: 6506651Abstract: There are provide a semiconductor device capable of increasing the operating speed of MOS transistors and improving current driving capability, and a method of manufacturing such a semiconductor device. A semiconductor device comprises a silicon substrate (1), an element isolation insulation film (2), a gate structure selectively formed on the main surface of the silicon substrate (1), and a sidewall (6) formed on the side face of the gate structure. The gate structure has a laminated structure with a gate insulation film (3) formed of a silicon oxide film, a gate electrode (4) formed of polysilicon, and a cobalt silicide layer (5) stacked in this order.Type: GrantFiled: November 9, 2001Date of Patent: January 14, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hirokazu Sayama, Hidekazu Oda, Yukio Nishida, Toshiyuki Oishi
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Publication number: 20020163036Abstract: A field-effect transistor including a gate electrode, silicon layers and source/drain regions is formed at a surface of a silicon substrate. Sidewall insulating films formed on the opposite side surfaces of the gate electrode are provided at portions located between the gate electrode and the silicon layers with voids, respectively. A semiconductor device having a field-effect transistor capable of fast operation is formed.Type: ApplicationFiled: September 18, 2001Publication date: November 7, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Naruhisa Miura, Toshiyuki Oishi, Yuji Abe, Kohei Sugihara
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Publication number: 20020158292Abstract: A semiconductor device that makes it possible to restrain the increase of the junction capacitance and others while preventing the punch-through and others accompanying the scale reduction, and a production method thereof are obtained. The semiconductor device includes source and drain regions of first conductivity type disposed to sandwich a channel region, and a pair of pocket injection regions of second conductivity type that cover only a neighborhood of side surface parts of the source and drain regions on the channel region side and respectively form a junction only between the neighborhood of the side surface parts and the pocket injection regions.Type: ApplicationFiled: June 19, 2002Publication date: October 31, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Yuji Abe, Naruhisa Miura, Kohei Sugihara, Toshiyuki Oishi, Yasunori Tokuda