Patents by Inventor Toshiyuki Oishi
Toshiyuki Oishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20020047163Abstract: There are provide a semiconductor device capable of increasing the operating speed of MOS transistors and improving current driving capability, and a method of manufacturing such a semiconductor device. A semiconductor device comprises a silicon substrate (1), an element isolation insulation film (2), a gate structure selectively formed on the main surface of the silicon substrate (1), and a sidewall (6) formed on the side face of the gate structure. The gate structure has a laminated structure with a gate insulation film (3) formed of a silicon oxide film, a gate electrode (4) formed of polysilicon, and a cobalt silicide layer (5) stacked in this order.Type: ApplicationFiled: November 9, 2001Publication date: April 25, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hirokazu Sayama, Hidekazu Oda, Yukio Nishida, Toshiyuki Oishi
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Publication number: 20020045317Abstract: Source/drain regions are formed with two regions of an epitaxial silicon film formed on the surface of the substrate and a region formed by ion implantation and thermal diffusion of impurities into the substrate, and the depth of junction of the source/drain regions is formed at a depth identical with or shallower than the depth of junction of the extension regions. As a result, even if the thickness of the side wall layer is reduced, since the depletion layer of the extension regions with lower impurity concentration compared with the source/drain regions is predominant, the short channel effect are less degraded.Type: ApplicationFiled: September 19, 2001Publication date: April 18, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Toshiyuki Oishi, Kohei Sugihara, Naruhisa Miura, Yuji Abe, Yasunori Tokuda
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Publication number: 20020037619Abstract: A dummy gate electrode is formed before the gate electrode is formed. Extension regions, side wall silicon nitride film, source/drain regions, silicon oxide film, and others are formed with respect to the dummy gate electrode. The dummy gate electrode is removed, and a part of the extension regions diffused to a region immediately under the dummy gate electrode is removed. The removed part is filled with silicon selection epitaxial film. Thereafter, the intended gate electrode is formed. This production method gives a semiconductor device that prevents the deterioration of electrical characteristics caused by short channel effect and parasitic resistance.Type: ApplicationFiled: March 16, 2001Publication date: March 28, 2002Inventors: Kohei Sugihara, Toshiyuki Oishi, Naruhisa Miura, Yuji Abe, Yasunori Tokuda
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Patent number: 6344388Abstract: In a method of manufacturing a semiconductor device capable of reducing gate resistance by increasing the width of a conductive layer formed on a gate electrode without increasing the gate length, an extension is formed in an upper surface of a silicon substrate, and thereafter a silicon oxide film and a silicon nitride film are deposited on the overall surface. Then, the silicon nitride film and the silicon oxide film are anisotropically etched in this order. Then, another silicon oxide film is deposited on the overall surface and thereafter anisotropically etched. Then, ion implantation is performed through a gate electrode and a side wall serving as masks, to form an impurity region. Silicon is grown under conditions having selectivity for a silicon oxide film, to form a silicon growth layer. Then, cobalt is deposited on the overall surface and thereafter heat treatment is performed to form a cobalt silicide layer. Thereafter unreacted cobalt is removed.Type: GrantFiled: June 4, 1999Date of Patent: February 5, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshiyuki Oishi, Yukio Nishida, Hirokazu Sayama
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Publication number: 20020011635Abstract: A semiconductor device that makes it possible to restrain the increase of the junction capacitance and others while preventing the punch-through and others accompanying the scale reduction, and a production method thereof are obtained. The semiconductor device includes source and drain regions of first conductivity type disposed to sandwich a channel region, and a pair of pocket injection regions of second conductivity type that cover only a neighborhood of side surface parts of the source and drain regions on the channel region side and respectively form a junction only between the neighborhood of the side surface parts and the pocket injection regions.Type: ApplicationFiled: December 14, 2000Publication date: January 31, 2002Inventors: Yuji Abe, Naruhisa Miura, Kohei Sugihara, Toshiyuki Oishi, Yasunori Tokuda
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Publication number: 20020006706Abstract: Nitrogen distributed layers 3N and 53N are formed in the vicinity of surfaces of silicon layers 3 and 53 on the silicide layer 11 and 61 sides, respectively. When ions are implanted for forming source/drain regions 9 and 59, a dopant is also implanted into the silicon layers 3 and 53. Consequently, a boron distributed layer 3B or a phosphorus distributed layer 53P is formed in a deeper region than the nitrogen distributed layers 3N and 53N. Cobalt is deposited to cover the silicon layers 3 and 53 and p+-type layers 8 and 58, and silicide layers 11, 61, 10 and 60 are thus formed by a salicide reaction. Interaction of boron and phosphorus (interaction of the dopant in the silicon layer with the silicide layer during a salicide reaction) is suppressed by nitrogen in the nitrogen distributed layers 3N and 53N. As a result, a MOS transistor which comprises gate electrodes 5 and 55 having low resistances and has a predetermined threshold is manufactured.Type: ApplicationFiled: September 16, 1999Publication date: January 17, 2002Inventors: YUKIO NISHIDA, HIROKAZU SAYAMA, TOSHIYUKI OISHI
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Patent number: 6335252Abstract: An MIS transistor manufacturing method which can prevent unwanted diffusion of extensions caused by the drive to the source/drain so that the diffusion of the source/drain and the diffusion of the extensions can independently be controlled so as to obtain optimum structure for each. Source/drain are formed by ion implantation using, as a mask, L-shaped silicon nitride films formed on sides of a gate electrode and silicon oxide films covering the silicon nitride films. The silicon oxide films are then removed leaving the silicon nitride films. Impurity ions are then ion-implanted into the main surface of the silicon substrate through the silicon nitride films. Since the silicon nitride films are thicker in the vicinity of the gate electrode and thinner in the vicinity of the source/drain, this process forms extensions penetrating under the gate electrode for a small distance.Type: GrantFiled: May 4, 2000Date of Patent: January 1, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshiyuki Oishi, Yukio Nishida, Hirokazu Sayama, Hidekazu Oda
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Patent number: 6245641Abstract: A first trench having a first width and a second trench having a width which is smaller than the first width are formed on a major surface of a semiconductor substrate. A first isolation insulator having an outer side wall is formed to fill up the first trench. A second isolation insulator having an outer side wall is formed to fill up the second trench. The first isolation insulator includes a side wall insulator film forming the outer side wall and an internal insulator film enclosed with the side wall insulator film for filling up the first trench. The second isolation insulator includes an internal insulator film forming the outer side wall for filling up the second trench. Thus obtained are a highly reliable semiconductor device comprising isolation insulators having different widths and a method of fabricating the same.Type: GrantFiled: July 16, 1998Date of Patent: June 12, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsuomi Shiozawa, Toshiyuki Oishi
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Patent number: 6110291Abstract: A thin film forming apparatus using laser includes a chamber (1), a target (5) placed therein, a laser light source (10) for emitting laser beam to target (5), and a substrate holder (3). When target (5) is irradiated with laser beam (16), a plume (15) is generated, and materials included in plume (15) are deposited on the surface of a substrate (2) held by substrate holder (3). The laser beam emitted from laser light source (10) has its cross section shaped to a desired shape when passed through a shielding plate (4804), for example, so that the surface of the target (5) is irradiated with the beam having uniform light intensity distribution. Therefore, a plume (15) having uniform density distribution of active particles is generated, and therefore a thin film of high quality can be formed over a wide area with uniform film quality, without damaging the substrate.Type: GrantFiled: August 7, 1996Date of Patent: August 29, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kenyu Haruta, Koichi Ono, Hitoshi Wakata, Mutsumi Tsuda, Yoshio Saito, Keisuke Nanba, Kazuyoshi Kojima, Tetsuya Takami, Akihiro Suzuki, Tomohiro Sasagawa, Kenichi Kuroda, Toshiyuki Oishi, Yukihiko Wada, Akihiko Furukawa, Yasuji Matsui, Akimasa Yuki, Takaaki Kawahara, Hideki Yabe, Taisuke Furukawa, Kouji Kise, Noboru Mikami, Tsuyoshi Horikawa, Tetsuo Makita, Kazuo Kuramoto, Naohiko Fujino, Hiroshi Kuroki, Tetsuo Ogama, Junji Tanimura
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Patent number: 6081662Abstract: In a trench isolation structure having active regions at a main surface of a silicon substrate isolated by providing a gate electrode on an insulation film formed in a trench with a gate oxide film thereunder, the insulation film has a vertical cross section configuration wherein the carrier concentration of the active region at the proximity of the upper edge corner of the trench becomes lower than the carrier concentration at the center of the active region in a state where a predetermined bias voltage is applied to the gate electrode. According to this structure, electric field concentration at the edge of the trench isolation can be relaxed and generation of an inverse narrow channel effect suppressed. Therefore, the subthreshold characteristics can be improved.Type: GrantFiled: September 29, 1997Date of Patent: June 27, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takaaki Murakami, Kenji Yasumura, Toshiyuki Oishi, Katsuomi Shiozawa
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Patent number: 5622567Abstract: A thin film forming apparatus using laser includes a chamber (1), a target (5) placed therein, a laser light source (10) for emitting laser beam to target (5), and a substrate holder (3). When target (5) is irradiated with laser beam (16), a plume (15) is generated, and materials included in plume (15) are deposited on the surface of a substrate (2) held by substrate holder (3). The laser beam emitted from laser light source (10) has its cross section shaped to a desired shape when passed through a shielding plate (4804), for example, so that the surface of the target (5) is irradiated with the beam having uniform light intensity distribution. Therefore, a plume (15) having uniform density distribution of active particles is generated, and therefore a thin film of high quality can be formed over a wide area with uniform film quality, without damaging the substrate.Type: GrantFiled: November 29, 1993Date of Patent: April 22, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuyoshi Kojima, Tetsuya Takami, Kenichi Kuroda, Toshiyuki Oishi, Yukihiko Wada, Akihiko Furukawa
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Patent number: 5020072Abstract: A semiconductor laser device includes an active layer, a first semiconductor layer having a larger energy band gap than the active layer, a diffraction grating layer having a larger energy band gap than the active layer and a smaller energy band gap than the first semiconductor layer, and a second semiconductor layer having the same composition as the first semiconductor layer, successively grown on the active layer, parallel stripe grooves of predetermined period reaching the first semiconductor layer produced at the entire surface of the grown layers, a cladding layer having the same composition as the first semiconductor layer which is re-grown thereon, and a diffraction grating constituted by the remainder of the diffraction grating layer. The coupling coefficient of the light is determined by the film thickness of a layer produced between the active layer and the diffraction grating layer, and the amplitude of the diffraction grating is determined by the layer thickness of the diffraction grating layer.Type: GrantFiled: September 1, 1989Date of Patent: May 28, 1991Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yuji Abe, Hiroshi Sugimoto, Kenichi Ohtsuka, Toshiyuki Oishi, Teruhito Matsui