Patents by Inventor Travis J. Anderson

Travis J. Anderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136180
    Abstract: A method for growing nanocrystalline diamond (NCD) on Ga2O3 to provide thermal management in Ga2O3-based devices. A protective SiNx interlayer is deposited on the Ga2O3 before growth of the NCD layer to protect the Ga2O3 from damage caused during growth of the NCD layer. The presence of the NCD provides thermal management and enables improved performance of the Ga2O3-based device.
    Type: Application
    Filed: October 19, 2023
    Publication date: April 25, 2024
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Marko J. Tadjer, Joseph A. Spencer, Alan G. Jacobs, Hannah N. Masten, James Spencer Lundh, Karl D. Hobart, Travis J. Anderson, Tatyana I. Feygelson, Bradford B. Pate, Boris N. Feigelson
  • Publication number: 20240120201
    Abstract: A technique for selective-area diffusion doping of III-N epitaxial material layers and for fabricating power device structures utilizing this technique. Dopant species such as Mg are introduced into the III-N material layer and are diffused into the III-N material by annealing under stable or metastable conditions. The dopant species can be introduced via deposition of a metal or alloy layer containing such species using sputtering, e-beam evaporation or other technique known to those skilled in the art. The dopant material layer is capped with a thermally stable layer to prevent decomposition and out-diffusion, and then is annealed under stable or metastable conditions to diffuse the dopant into the III-N material GaN without decomposing the surface.
    Type: Application
    Filed: March 31, 2023
    Publication date: April 11, 2024
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Travis J. Anderson, Mona A. Ebrish, Alan G. Jacobs, Karl D. Hobart, Francis J. Kub
  • Publication number: 20240097064
    Abstract: A light controlled semiconductor switch (LCSS), method of making, and method of using are provided. In embodiments, a vertical LCSS includes: a semiconductor body including a photoactive layer of gallium nitride (GaN) doped with carbon; a first electrode in contact with a first surface of the semiconductor body, the first electrode defining an area through which light energy from at least one light source can impinge on the first surface; and a second electrode in contact with a second surface of the semiconductor body opposed to the first surface, wherein the vertical LCSS is configured to switch from a non-conductive off-state to a conductive on-state when the light energy impinging on the semiconductor body is sufficient to raise electrons within the photoactive layer into a conduction band of the photoactive layer.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 21, 2024
    Inventors: Andrew D. Koehler, Travis J. Anderson, Geoffrey M. Foster, Karl D. Hobart, Francis J. Kub, Michael A. Mastro
  • Patent number: 11817318
    Abstract: A method for activating implanted dopants and repairing damage to dopant-implanted GaN to form n-type or p-type GaN. A GaN substrate is implanted with n- or p-type ions and is subjected to a high-temperature anneal to activate the implanted dopants and to produce planar n- or p-type doped areas within the GaN having an activated dopant concentration of about 1018-1022 cm?3. An initial annealing at a temperature at which the GaN is stable at a predetermined process temperature for a predetermined time can be conducted before the high-temperature anneal. A thermally stable cap can be applied to the GaN substrate to suppress nitrogen evolution from the GaN surface during the high-temperature annealing step. The high-temperature annealing can be conducted under N2 pressure to increase the stability of the GaN. The annealing can be conducted using laser annealing or rapid thermal annealing (RTA).
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: November 14, 2023
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Travis J. Anderson, James C. Gallagher, Marko J. Tadjer, Alan G. Jacobs, Boris N. Feigelson
  • Publication number: 20230207323
    Abstract: A method for activating implanted dopants and repairing damage to dopant-implanted GaN to form n-type or p-type GaN. A GaN substrate is implanted with n- or p-type ions and is subjected to a high-temperature anneal to activate the implanted dopants and to produce planar n- or p-type doped areas within the GaN having an activated dopant concentration of about 1018-1022 cm?3. An initial annealing at a temperature at which the GaN is stable at a predetermined process temperature for a predetermined time can be conducted before the high-temperature anneal. A thermally stable cap can be applied to the GaN substrate to suppress nitrogen evolution from the GaN surface during the high-temperature annealing step. The high-temperature annealing can be conducted under N2 pressure to increase the stability of the GaN. The annealing can be conducted using laser annealing or rapid thermal annealing (RTA).
    Type: Application
    Filed: March 1, 2023
    Publication date: June 29, 2023
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Travis J. Anderson, James C. Gallagher, Marko J. Tadjer, Alan G. Jacobs, Boris N. Feigelson
  • Publication number: 20230197534
    Abstract: A computer-implemented method for evaluating a semiconductor wafer. In accordance with the present invention, using a properly designed neural network, the computer can take image data regarding the wafer at issue, plus image and electrical data regarding a prior wafer and devices fabricated on the prior wafer, to find relations to and between structural features, both known and previously unidentified, that can degrade the performance of devices fabricated on the wafer and/or can reduce the device yield of the wafer.
    Type: Application
    Filed: November 4, 2022
    Publication date: June 22, 2023
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Michael A. Mastro, James Gallagher, Travis J. Anderson
  • Patent number: 11634834
    Abstract: A method for growing polycrystalline diamond films having engineered grain growth and microstructure. Grain growth of a polycrystalline diamond film on a substrate is manipulated by growing the diamond on a nanopatterned substrate having features on the order of the initial grain size of the diamond film. By growing the diamond on such nanopatterned substrates, the crystal texture of a polycrystalline diamond film can be engineered to favor the preferred <110> orientation texture, which in turn enhances the thermal conductivity of the diamond film.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: April 25, 2023
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Karl D. Hobart, Tatyana I. Feygelson, Marko J. Tadjer, Travis J. Anderson, Andrew D. Koehler, Samuel Graham, Jr., Mark Goorsky, Zhe Cheng, Luke Yates, Tingyu Bai, Yekan Wang
  • Publication number: 20230030549
    Abstract: A hybrid edge termination structure and method of forming the same. The hybrid edge termination structure in accordance with the invention is based on a junction termination extension (JTE) architecture, but includes an additional Layer of guard ring (GR) structures to further implement the implantation of dopants into the structure. The hybrid edge termination structure of the invention has a three-Layer structure, with a top Layer and a bottom Layer each having a constant dopant concentration in the lateral direction, and a middle Layer consisting of a plurality of spatially defined alternating regions that exhibit the electrical properties of either the top or bottom layer. By including the second layer, a discretized varying charge profile can be obtained that approximates the varying charge profile obtained using tapered edge termination but with easier manufacturing and lower cost.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 2, 2023
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Travis J. Anderson, Mona A. Ebrish, Andrew D. Koehler, Alan G. Jacobs, Matthew A. Porter, Karl D. Hobart, Prakash Pandey, Tolen Michael Nelson, Daniel G. Georgiev, Raghav Khanna, Michael Robert Hontz
  • Patent number: 11532478
    Abstract: A method for activating implanted dopants and repairing damage to dopant-implanted GaN to form n-type or p-type GaN. A GaN substrate is implanted with n- or p-type ions and is subjected to a high-temperature anneal to activate the implanted dopants and to produce planar n- or p-type doped areas within the GaN having an activated dopant concentration of about 1018-1022 cm?3. An initial annealing at a temperature at which the GaN is stable at a predetermined process temperature for a predetermined time can be conducted before the high-temperature anneal. A thermally stable cap can be applied to the GaN substrate to suppress nitrogen evolution from the GaN surface during the high-temperature annealing step. The high-temperature annealing can be conducted under N2 pressure to increase the stability of the GaN. The annealing can be conducted using laser annealing or rapid thermal annealing (RTA).
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: December 20, 2022
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Travis J. Anderson, James C. Gallagher, Marko J. Tadjer, Alan G. Jacobs, Boris N. Feigelson
  • Patent number: 11415518
    Abstract: A method for mapping and analyzing a GaN substrate to identify areas of the substrate suitable for fabrication of electronic devices thereon. Raman spectroscopy is performed over the surface of a GaN substrate to produce maps of the E2 and A1 peaks at a plurality of areas on the substrate surface, the E2 and A1 peaks being associated with known concentrations of defects and charge carriers, so that areas of the GaN substrate having relatively high resistivity or conductivity which make those areas suitable or unsuitable for fabrication of electronic devices can be identified. The devices can then be fabricated only on suitable areas of the substrate, or the size of the devices can be tailored to maximize the yield of devices fabricated thereon. Substrates not meeting a threshold level of defect and/or charge carrier concentration can be discarded without fabrication of poor-quality devices thereon.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: August 16, 2022
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Travis J. Anderson, Jennifer K. Hite, James C. Gallagher, Karl D. Hobart
  • Publication number: 20220254639
    Abstract: A method for activating implanted dopants and repairing damage to dopant-implanted GaN to form n-type or p-type GaN. A GaN substrate is implanted with n- or p-type ions and is subjected to a high-temperature anneal to activate the implanted dopants and to produce planar n- or p-type doped areas within the GaN having an activated dopant concentration of about 1018-1022 cm?3. An initial annealing at a temperature at which the GaN is stable at a predetermined process temperature for a predetermined time can be conducted before the high-temperature anneal. A thermally stable cap can be applied to the GaN substrate to suppress nitrogen evolution from the GaN surface during the high-temperature annealing step. The high-temperature annealing can be conducted under N2 pressure to increase the stability of the GaN. The annealing can be conducted using laser annealing or rapid thermal annealing (RTA).
    Type: Application
    Filed: January 26, 2022
    Publication date: August 11, 2022
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Travis J. Anderson, James C. Gallagher, Marko J. Tadjer, Alan G. Jacobs, Boris N. Feigelson
  • Patent number: 11342420
    Abstract: Current conducting devices and methods for their formation are disclosed. Described are vertical current devices that include a substrate, an n-type material layer, a plurality of p-type gates, and a source. The n-type material layer disposed on the substrate and includes a current channel. A plurality of p-type gates are disposed on opposite sides of the current channel. A source is disposed on a distal side of the current channel with respect to the substrate. The n-type material layer comprises beta-gallium oxide.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: May 24, 2022
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis J. Anderson, Marko J. Tadjer, Andrew D. Koehler, Karl D. Hobart
  • Publication number: 20220069668
    Abstract: An example electric motor includes a housing, a stator fixed relative to the housing, a rotor, a brake assembly, a first bearing, and a second bearing. The rotor has a hub portion, a cylindrical portion, and a disk portion. The hub portion of the rotor has a first end, a second end, and a through hole therethrough. The brake assembly is fixed relative to the housing and configured to selectively couple the disk portion of the rotor to the housing. The first bearing is mounted between the first end of the hub portion of the rotor and the disk portion of the rotor. The second bearing is mounted between the second end of the hub portion of the rotor and the disk portion of the rotor.
    Type: Application
    Filed: April 17, 2020
    Publication date: March 3, 2022
    Inventors: Steven R. Huard, Travis J. Anderson, Kevin B. Henke, Joseph L. Dobmeier, John P. Blomberg, Justin O. Byers
  • Publication number: 20220059352
    Abstract: A method for activating implanted dopants and repairing damage to dopant-implanted GaN to form n-type or p-type GaN. A GaN substrate is implanted with n- or p-type ions and is subjected to a high-temperature anneal to activate the implanted dopants and to produce planar n- or p-type doped areas within the GaN having an activated dopant concentration of about 1018-1022 cm?3. An initial annealing at a temperature at which the GaN is stable at a predetermined process temperature for a predetermined time can be conducted before the high-temperature anneal. A thermally stable cap can be applied to the GaN substrate to suppress nitrogen evolution from the GaN surface during the high-temperature annealing step. The high-temperature annealing can be conducted under N2 pressure to increase the stability of the GaN. The annealing can be conducted using laser annealing or rapid thermal annealing (RTA).
    Type: Application
    Filed: November 8, 2021
    Publication date: February 24, 2022
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Travis J. Anderson, James C. Gallagher, Marko J. Tadjer, Alan G. Jacobs, Boris N. Feigelson
  • Publication number: 20220059353
    Abstract: A method for activating implanted dopants and repairing damage to dopant-implanted GaN to form n-type or p-type GaN. A GaN substrate is implanted with n- or p-type ions and is subjected to a high-temperature anneal to activate the implanted dopants and to produce planar n- or p-type doped areas within the GaN having an activated dopant concentration of about 1018-1022 cm?3. An initial annealing at a temperature at which the GaN is stable at a predetermined process temperature for a predetermined time can be conducted before the high-temperature anneal. A thermally stable cap can be applied to the GaN substrate to suppress nitrogen evolution from the GaN surface during the high-temperature annealing step. The high-temperature annealing can be conducted under N2 pressure to increase the stability of the GaN. The annealing can be conducted using laser annealing or rapid thermal annealing (RTA).
    Type: Application
    Filed: November 8, 2021
    Publication date: February 24, 2022
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Travis J. Anderson, James C. Gallagher, Marko J. Tadjer, Alan G. Jacobs, Boris N. Feigelson
  • Patent number: 11227943
    Abstract: A high electron mobility transistor (HEMT) and method of producing the same are provided. The HEMT includes a barrier layer formed on a GaN layer. The HEMT also includes a ZrO2 gate dielectric layer formed by either a ZTB precursor, a TDMA-Zr precursor, or both. The HEMT may also include a recess in the barrier layer in the gate region of the HEMT. The HEMTs may operate in an enhancement mode.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: January 18, 2022
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Travis J. Anderson, Virginia D. Wheeler, Karl D. Hobart, Francis J. Kub
  • Publication number: 20210389126
    Abstract: An improved method for evaluating GaN wafers. RMS analysis of wafer heights obtained by optical interferometric profilometry is combined with an extreme Studentized deviate (ESD) analysis to obtain a map of the wafer surface that more accurately identifies areas on the surface of a GaN wafer having defects that making those areas unsuitable for fabrication of a vertical electronic device thereon such as bumps and/or pits that can lower the breakdown voltage, increase the on-resistance, and increase the ideality factor.
    Type: Application
    Filed: June 11, 2021
    Publication date: December 16, 2021
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: James C. Gallagher, Travis J. Anderson, Jennifer K. Hite, Karl D. Hobart
  • Patent number: 11201058
    Abstract: A method for activating implanted dopants and repairing damage to dopant-implanted GaN to form n-type or p-type GaN. A GaN substrate is implanted with n- or p-type ions and is subjected to a high-temperature anneal to activate the implanted dopants and to produce planar n- or p-type doped areas within the GaN having an activated dopant concentration of about 1018-1022 cm?3. An initial annealing at a temperature at which the GaN is stable at a predetermined process temperature for a predetermined time can be conducted before the high-temperature anneal. A thermally stable cap can be applied to the GaN substrate to suppress nitrogen evolution from the GaN surface during the high-temperature annealing step. The high-temperature annealing can be conducted under N2 pressure to increase the stability of the GaN. The annealing can be conducted using laser annealing or rapid thermal annealing (RTA).
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: December 14, 2021
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Travis J. Anderson, James C. Gallagher, Marko J. Tadjer, Alan G. Jacobs, Boris N. Feigelson
  • Publication number: 20210381127
    Abstract: A method for growing polycrystalline diamond films having engineered grain growth and microstructure. Grain growth of a polycrystalline diamond film on a substrate is manipulated by growing the diamond on a nanopatterned substrate having features on the order of the initial grain size of the diamond film. By growing the diamond on such nanopatterned substrates, the crystal texture of a polycrystalline diamond film can be engineered to favor the preferred <110> orientation texture, which in turn enhances the thermal conductivity of the diamond film.
    Type: Application
    Filed: August 24, 2021
    Publication date: December 9, 2021
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Karl D. Hobart, Tatyana I. Feygelson, Marko J. Tadjer, Travis J. Anderson, Andrew D. Koehler, Samuel Graham, JR., Mark Goorsky, Zhe Cheng, Luke Yates, Tingyu Bai, Yekan Wang
  • Publication number: 20210375680
    Abstract: Methods for obtaining a free-standing thick (>5 ?m) epitaxial material layer or heterostructure stack and for transferring the thick epitaxial layer or stack to an arbitrary substrate. A thick epitaxial layer or heterostructure stack is formed on an engineered substrate, with a sacrificial layer disposed between the epitaxial layer and the engineered substrate. When the sacrificial layer is removed, the epitaxial layer becomes a thick freestanding layer that can be transferred to an arbitrary substrate, with the remaining engineered substrate being reusable for subsequent material layer growth. In an exemplary case, the material layer is a GaN layer and can be selectively bonded to an arbitrary substrate to selectively produce a Ga-polar or an N-polar GaN layer.
    Type: Application
    Filed: May 24, 2021
    Publication date: December 2, 2021
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Travis J. Anderson, Marko J. Tadjer, Karl D. Hobart