Abstract: An integrated circuit including a sense amplifier connected to a sense line is provided. The sense amplifier is configured to end a precharge phase of the sense line based on a state of the sense amplifier.

Abstract: A device includes a device casing and a water-soluble circuit located within the device casing. An identification code is encoded on the circuit. The identification code is associated with the device.

Abstract: Low leakage CAMs and method of searching low leakage CAMs. The method includes performing a pre-search and compare on a small number of pre-search bits with pre-search CAM cells powered to normal voltage levels at all times while the main-search CAM cells are powered to a lower voltage level. Only if a match is detected on the pre-search bits are the main-search CAM cells powered-up to normal voltage levels and the search of the main-search bits activated. The main-search CAM cells are powered to normal voltage levels during read and write operations.

Abstract: A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.

Abstract: An embodiment of the current disclosure is directed to a Static Random Access Memory (SRAM) device, and a design structure for the SRAM device. The SRAM device may include one or more SRAM cells. Each SRAM cell may further include a first and a second CMOS inverter that are cross-coupled. The first and second CMOS inverters may each have a first switch and a second switch. The SRAM device may also include a reset circuit. The reset circuit may be coupled to a first node of the first switch of the first CMOS inverter. The reset circuit may drive the first CMOS inverter to output a logical high signal in a reset mode.

Abstract: Disclosed are a memory system and an associated operating method. In the system, a first memory array comprises first memory cells requiring a range of time delays between wordline activating and bitline sensing. A delay signal generator delays an input signal by a selected time delay (i.e., a long time delay corresponding to statistically slow memory cells) and outputs a delay signal for read operation timing to ensure read functionality for statistically slow and faster memory cells. To accomplish this, the delay signal generator comprises a second memory array having second memory cells with the same design as the first memory cells. Transistors within the second memory cells are controlled by a lower gate voltage than transistors within the first memory cells in order to mimic the effect of higher threshold voltages, which result in longer time delays and which can be associated with the statistically slow first memory cells.

Abstract: A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line. In addition the SRAM may include a global bit line discharge logic connected with the global bit line and the local bit line. The global bit line discharge logic is adapted to draw the global bit line to a voltage below a precharge voltage and above a ground voltage during a read operation.

Abstract: A static random access memory (SRAM) includes a column of SRAM memory cells. The SRAM may include a circuit to copy a value stored in any SRAM memory cell in a column of SRAM memory cells to any SRAM memory cell in the column of SRAM memory cells in a single cycle of the SRAM.

Abstract: Embodiments of the disclosure provide a method for removing residual BPA from a residual BPA-containing substance and a method for making a container with residual BPA removed. The method may consist of preparing a stabilization reagent, wherein water is removed from the stabilization reagent. The method may also include preparing the residual BPA-containing substance. The method may also include reacting the residual BPA-containing substance in a melt condensation process with the stabilization reagent, wherein the stabilization reagent is non-toxic.

Abstract: Low leakage CAMs and method of searching low leakage CAMs. The method includes performing a pre-search and compare on a small number of pre-search bits with pre-search CAM cells powered to normal voltage levels at all times while the main-search CAM cells are powered to a lower voltage level. Only if a match is detected on the pre-search bits are the main-search CAM cells powered-up to normal voltage levels and the search of the main-search bits activated. The main-search CAM cells are powered to normal voltage levels during read and write operations.

Abstract: A static random access memory (SRAM) having two or more SRAM memory cells connected with a write bit line (WBL) and a write bit line complement (WBLC) is disclosed. The SRAM may include a write driver logic coupled to the WBL and the WBLC. The write driver logic is adapted to drive a selected bit line of the WBL and the WBLC to a voltage uplevel below a first supply voltage and shut off the drive to the selected bit line when the selected bit line reaches the uplevel. The write driver logic is further adapted to drive an unselected bit line of the WBL and the WBLC to a downlevel, in conjunction with the driving of the selected bit line to the uplevel, where the downlevel is a second supply voltage lower than the first supply voltage.

Abstract: A clock system includes a local clock buffer adapted to receive a variable global clock signal. The local clock buffer produces a first local clock signal from the variable global clock signal. The clock system includes a pulse width logic control circuit in operable communication with the local clock buffer. The pulse width logic control circuit may be adapted to limit the first local clock signal pulse width to be less than the variable global clock signal pulse width during a slow mode. The pulse width logic control circuit may be adapted to expand the first local clock signal pulse width to be greater than the variable global clock signal pulse width during a fast mode. The limited and expanded first local clock signals may signal a local evaluation circuit to address a memory line.

Abstract: A semiconductor device may include a through substrate via (TSV) conductive structure that may extend vertically through two or more layers of the semiconductor device. The TSV conductive structure may be coupled to a first voltage supply. The semiconductor device may include substrate layer. The substrate layer may include a first dopant region and a second dopant region. The first dopant region may be coupled to a second voltage supply. The second dopant region may be in electrical communication with the TSV conductive structure. The semiconductor device may include a first metal layer and a first insulator layer disposed between the substrate layer and the first metal layer. The first metal layer may laterally contact the TSV conductive structure. The first and second voltage supply may be adapted to create a capacitance at a junction between the first dopant region and the second dopant region.

Abstract: A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a precharge device connected between a voltage supply and the local bit line, and global bit line (GBL) discharge logic connected between a local bit line and a GBL. The GBL discharge logic transfers a logic value of the local bit line to the GBL during a read operation. GBL precharge logic connects the GBL to a global precharge input. The GBL precharge logic is adapted to draw the GBL to a precharge voltage above a discharge voltage and below a supply voltage during a precharge operation.

Abstract: A semiconductor device may include a through substrate via (TSV) conductive structure that may extend vertically through two or more layers of the semiconductor device. The TSV conductive structure may be coupled to a first voltage supply. The semiconductor device may include substrate layer. The substrate layer may include a first dopant region and a second dopant region. The first dopant region may be coupled to a second voltage supply. The second dopant region may be in electrical communication with the TSV conductive structure. The semiconductor device may include a first metal layer and a first insulator layer disposed between the substrate layer and the first metal layer. The first metal layer may laterally contact the TSV conductive structure. The first and second voltage supply may be adapted to create a capacitance at a junction between the first dopant region and the second dopant region.

Abstract: A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a precharge device connected between a voltage supply and the local bit line, and global bit line (GBL) discharge logic connected between a local bit line and a GBL. The GBL discharge logic transfers a logic value of the local bit line to the GBL during a read operation. GBL precharge logic connects the GBL to a global precharge input. The GBL precharge logic is adapted to draw the GBL to a precharge voltage above a discharge voltage and below a supply voltage during a precharge operation.

Abstract: A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value.

Abstract: Disclosed are a memory system and an associated operating method. In the system, a first memory array comprises first memory cells requiring a range of time delays between wordline activating and bitline sensing. A delay signal generator delays an input signal by a selected time delay (i.e., a long time delay corresponding to statistically slow memory cells) and outputs a delay signal for read operation timing to ensure read functionality for statistically slow and faster memory cells. To accomplish this, the delay signal generator comprises a second memory array having second memory cells with the same design as the first memory cells. Transistors within the second memory cells are controlled by a lower gate voltage than transistors within the first memory cells in order to mimic the effect of higher threshold voltages, which result in longer time delays and which can be associated with the statistically slow first memory cells.

Abstract: A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line. In addition the SRAM may include a global bit line discharge logic connected with the global bit line and the local bit line. The global bit line discharge logic is adapted to draw the global bit line to a voltage below a precharge voltage and above a ground voltage during a read operation.

Abstract: A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line. In addition the SRAM may include a global bit line discharge logic connected with the global bit line and the local bit line. The global bit line discharge logic is adapted to draw the global bit line to a voltage below a precharge voltage and above a ground voltage during a read operation.