Patents by Inventor Travis R. Hebig

Travis R. Hebig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120069688
    Abstract: A method and a dynamic Static Random Access Memory (SRAM) circuit for implementing single bit redundancy with any bit decode, and a design structure on which the subject circuit resides are provided. The SRAM circuit includes a plurality of bitline columns and a pair of redundancy columns respectively coupled to a respective merged bit column select and redundancy steering multiplexer. Each merged bit column select and redundancy steering multiplexer receives a respective select signal input. A select signal generation circuit receives a redundancy steering signal and a respective one-hot bit select signal, generating the respective select signal input.
    Type: Application
    Filed: September 21, 2010
    Publication date: March 22, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derick G. Behrends, Todd A. Christensen, Peter T. Freiburger, Travis R. Hebig, Jayson K. Wittrup
  • Patent number: 8108739
    Abstract: A method for allowing high-speed testability of a memory device having a core with memory cells for storing data, comprising: enabling a data signal having a first logical state or a second logical state from the core to reach an output port of the memory device within an evaluate cycle during a functional operating mode and pass an array built in self test during LBIST mode; enabling the data signal to change from the first logical state to the second logical state during LBIST mode at a time that coincides with the latest possible time the data signal from the core can reach the read output port within the evaluate cycle during the functional operating mode and pass the array built in self test; and executing a logic built-in self test configured to test a logic block located downstream of a transmission path of the memory device.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Chad A. Adams, Derick G. Behrends, Todd A. Christensen, Travis R. Hebig
  • Patent number: 7971164
    Abstract: A system, method and program product are described in which schematics in a library that a user has tagged are read as ready for layout. The difficulty of each layout is assessed based on statistics indicative of the complexity of the schematic. The statistics may regard the number of connections, pins, devices, and other schematic information. The information is used to calculate the total amount of effort required to complete the design and generate a report.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: June 28, 2011
    Assignee: International Business Machines Corporation
    Inventors: Derick G. Behrends, Travis R. Hebig, Daniel M. Nelson, Jesse D. Smith
  • Publication number: 20110109366
    Abstract: A delay circuit receives a data input having an input transition and that generates a data output having an output transition. The delay circuit is powered by a voltage source having a voltage. A first delay element is configured to generate a first data signal with a first edge that has a relatively constant delay relative to the input transition irrespective of the voltage of the voltage source. A second delay element is configured to generate a second data signal with a second edge that has a delay relative to the input transition as a function of the voltage of the voltage source. A selection element causes the output transition at the data output to correspond to a latest selected one of the first edge and the second edge. The delay circuit may be employed in a pulse generating circuit.
    Type: Application
    Filed: November 6, 2009
    Publication date: May 12, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Daniel M. Nelson
  • Patent number: 7782691
    Abstract: In a digital device for facilitating recovery of a precharged dot line, periodically precharged by a precharge signal, that has been prematurely discharged as a result of an early read condition, a data input signal can have a selected one of a first value and a second value. The first value is a value that would be reflected by the dot line being in a charged state. A logic device that is responsive to the data input signal causes charge to be applied to the dot line when the data signal has the first value.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: August 24, 2010
    Assignee: International Business Machines Corporation
    Inventors: Todd A. Christensen, Elizabeth L. Gerhard, Travis R. Hebig
  • Patent number: 7714630
    Abstract: The present disclosure is an apparatus for generating a decreasing delay with increasing input voltage to a predetermined voltage value at which point the delay may remain constant. The apparatus may include a circuit comprising a voltage regulator receiving an input voltage and two paths of inverters. At least two paths of inverters may be coupled to an input signal, the input signal may be low voltage (e.g. 0) or high voltage (e.g. 1). A first path may be referenced to a reference voltage while the second path may be referenced to the input voltage. The apparatus may include logic gates for receiving the output of each of the first path of inverters and the output of the second path of inverters to generate a desired output. As the input voltage increases, delay of the apparatus may decrease until the input voltage is approximately the same voltage as the reference voltage, at which the delay may remain constant.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: May 11, 2010
    Assignee: International Business Machines Corporation
    Inventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Daniel M. Nelson
  • Publication number: 20100030804
    Abstract: Embodiments of the invention provide techniques for synchronizing virtual locations to real locations. In one embodiment, data sources are monitored to detect events that affect real locations. A filter specified by an owner of the virtual location may be used to detect keywords indicating events affecting a particular location. In the event that such events are detected, the owner may be notified to modify the virtual location to match the real location. Optionally, the virtual location may be automatically modified to match the real location.
    Type: Application
    Filed: July 31, 2008
    Publication date: February 4, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derick G. Behrends, Zachary A. Garbow, Travis R. Hebig, Daniel M. Nelson, Jesse D. Smith
  • Publication number: 20090309644
    Abstract: The present disclosure is an apparatus for generating a decreasing delay with increasing input voltage to a predetermined voltage value at which point the delay may remain constant. The apparatus may include a circuit comprising a voltage regulator receiving an input voltage and two paths of inverters. At least two paths of inverters may be coupled to an input signal, the input signal may be low voltage (e.g. 0) or high voltage (e.g. 1). A first path may be referenced to a reference voltage while the second path may be referenced to the input voltage. The apparatus may include logic gates for receiving the output of each of the first path of inverters and the output of the second path of inverters to generate a desired output. As the input voltage increases, delay of the apparatus may decrease until the input voltage is approximately the same voltage as the reference voltage, at which the delay may remain constant.
    Type: Application
    Filed: June 13, 2008
    Publication date: December 17, 2009
    Applicant: International Business Machines Corporation
    Inventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Daniel M. Nelson
  • Publication number: 20090271669
    Abstract: A method for allowing high-speed testability of a memory device having a core with memory cells for storing data, comprising: enabling a data signal having a first logical state or a second logical state from the core to reach an output port of the memory device within an evaluate cycle during a functional operating mode and pass an array built in self test during LBIST mode; enabling the data signal to change from the first logical state to the second logical state during LBIST mode at a time that coincides with the latest possible time the data signal from the core can reach the read output port within the evaluate cycle during the functional operating mode and pass the array built in self test; and executing a logic built-in self test configured to test a logic block located downstream of a transmission path of the memory device.
    Type: Application
    Filed: April 28, 2008
    Publication date: October 29, 2009
    Inventors: Chad A. Adams, Derick G. Behrends, Todd A. Christensen, Travis R. Hebig
  • Publication number: 20090259977
    Abstract: A system, method and program product are described in which schematics in a library that a user has tagged are read as ready for layout. The difficulty of each layout is assessed based on statistics indicative of the complexity of the schematic. The statistics may regard the number of connections, pins, devices, and other schematic information. The information is used to calculate the total amount of effort required to complete the design and generate a report.
    Type: Application
    Filed: April 10, 2008
    Publication date: October 15, 2009
    Inventors: Derick G. Behrends, Travis R. Hebig, Daniel M. Nelson, Jesse D. Smith
  • Patent number: 7535776
    Abstract: A method for passing data from an input to an output of a domino read access path in domino read SRAM memory including receiving at least a portion of the input data from a latch configuration, gating a global precharge signal, gating a bit select circuitry signal, driving the input data statically through a transmission gate of a static bypass multiplexer to the global dot of the domino read SRAM memory, initiating a write around cycle signal, offsetting the write around signal input into the static bypass multiplexer and the precharge signal by at least one phase using a wave shaper, driving the input data from the global dot through a keeper circuit, and driving the input data from the keeper circuit to at least one NAND gate of a pair of cross-coupled NAND gates, the pair of cross-coupled NAND gates being configured in a transparent state.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: May 19, 2009
    Assignee: International Business Machines Corporation
    Inventors: Derick G. Behrends, Travis R. Hebig, Daniel M. Nelson, Jesse D. Smith
  • Publication number: 20090116324
    Abstract: In a digital device for facilitating recovery of a precharged dot line, periodically precharged by a precharge signal, that has been prematurely discharged as a result of an early read condition, a data input signal can have a selected one of a first value and a second value. The first value is a value that would be reflected by the dot line being in a charged state. A logic device that is responsive to the data input signal causes charge to be applied to the dot line when the data signal has the first value.
    Type: Application
    Filed: November 7, 2007
    Publication date: May 7, 2009
    Inventors: Todd A Christensen, Elizabeth L. Gerhard, Travis R. Hebig
  • Patent number: 7502276
    Abstract: A domino read SRAM capable of writing multiple wordlines simultaneously. A read/write multiplexer may allow conventional, single-wordline selection during a read operation, while allowing external logic, such as an ABIST controller, to enable multiple wordlines during a write operation.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: March 10, 2009
    Assignee: International Business Machines Corporation
    Inventors: Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Daniel M. Nelson