Patents by Inventor Trevor Nigel Mudge
Trevor Nigel Mudge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10579463Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.Type: GrantFiled: September 9, 2016Date of Patent: March 3, 2020Assignees: ARM Limited, The Regents of the University of MichiganInventors: Krisztian Flautner, Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge, David Bull
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Patent number: 10572334Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.Type: GrantFiled: October 12, 2015Date of Patent: February 25, 2020Assignees: ARM Limited, The Regents of the University of MichiganInventors: Krisztian Flautner, Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge, David Bull
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Patent number: 10037295Abstract: An interconnect within an integrated circuit provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).Type: GrantFiled: December 2, 2016Date of Patent: July 31, 2018Assignee: The Regents of the University of MichiganInventors: Supreet Jeloka, Sandunmalee Nilmini Abeyratne, Ronald George Dreslinski, Reetuparna Das, Trevor Nigel Mudge, David Theodore Blaauw
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Publication number: 20170083471Abstract: An interconnect within an integrated circuit provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).Type: ApplicationFiled: December 2, 2016Publication date: March 23, 2017Inventors: Supreet JELOKA, Sandunmalee Nilmini ABEYRATNE, Ronald George DRESLINSKI, Reetuparna DAS, Trevor Nigel MUDGE, David Theodore BLAAUW
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Publication number: 20160378588Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.Type: ApplicationFiled: September 9, 2016Publication date: December 29, 2016Inventors: KRISZTIAN FLAUTNER, TODD MICHAEL AUSTIN, DAVID THEODORE BLAAUW, TREVOR NIGEL MUDGE, DAVID BULL
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Patent number: 9514074Abstract: An interconnect within an integrated circuit provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).Type: GrantFiled: July 12, 2013Date of Patent: December 6, 2016Assignee: The Regents of the University of MichiganInventors: Supreet Jeloka, Sandunmalee Nilmini Abeyratne, Ronald George Dreslinski, Reetuparna Das, Trevor Nigel Mudge, David Theodore Blaauw
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Patent number: 9513959Abstract: A hardware transactional memory 12, 14, 16, 18, 20 is provided within a multiprocessor 4, 6, 8, 10 system with coherency control and hardware transaction memory control circuitry 22 that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data 26, 28, 30. The conflict data characterizes previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.Type: GrantFiled: April 24, 2008Date of Patent: December 6, 2016Assignees: ARM Limited, The Regents of the University of MichiganInventors: Stuart David Biles, Geoffrey Blake, Trevor Nigel Mudge
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Patent number: 9471480Abstract: A data processing apparatus has a memory rename table for storing memory rename entries each identifying a mapping between a memory address of a location in memory and a mapped register of a plurality of registers. The mapped register is identified by a register number. In response to a store instruction, the store target memory address of the store instruction is mapped to a store destination register and so the data value is stored to the store destination register instead of memory. A memory rename entry is provided in the table to identify the mapping between the store target memory address and store destination target register. In response to a load instruction, if there is a hit in the memory rename table for the load target memory address then the loaded value can be read from the mapped register instead of memory.Type: GrantFiled: February 21, 2014Date of Patent: October 18, 2016Assignee: The Regents of the University of MichiganInventors: Joseph Michael Pusdesris, Yiping Kang, Andrea Pellegrini, Benjamin Allen Vandersloot, Trevor Nigel Mudge
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Patent number: 9448875Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.Type: GrantFiled: December 6, 2013Date of Patent: September 20, 2016Assignees: ARM Limited, The Regents of the University of MichiganInventors: Krisztian Flautner, Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge, David Bull
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Publication number: 20160034339Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.Type: ApplicationFiled: October 12, 2015Publication date: February 4, 2016Inventors: Krisztian FLAUTNER, Todd Michael AUSTIN, David Theodore BLAAUW, Trevor Nigel MUDGE, David BULL
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Patent number: 9164842Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.Type: GrantFiled: June 25, 2013Date of Patent: October 20, 2015Assignees: ARM Limited, The Regents of the University of MichiganInventors: Krisztian Flautner, Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge, David Bull
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Patent number: 9135011Abstract: A data processing system 2 is provided with branch prediction circuitry 20 for performing branch prediction operations. Next branch table circuitry 22 stores data identifying from a given branch instruction what will be the address of the next branch instruction to be encountered within the program flow. This next branch instruction address is supplied to the branch prediction circuitry 20 which uses it to form its prediction prior to that next branch instruction being identified as such by the instruction decoder 16. This permits branch prediction to commence earlier in the branch prediction circuitry 20 than would otherwise be the case.Type: GrantFiled: April 30, 2012Date of Patent: September 15, 2015Assignee: The Regents of the University of MichiganInventors: David Thomas Manville, Trevor Nigel Mudge
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Publication number: 20150154045Abstract: A hardware transactional memory is provided within a multiprocessor system with coherency control and hardware transaction memory control circuitry that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data. The conflict data characterizes previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.Type: ApplicationFiled: February 10, 2015Publication date: June 4, 2015Inventors: Geoffrey Blake, Trevor Nigel Mudge, Nathan Yong Seng Chong, Ronald George Dreslinski, Stuart David Biles, Emre Özer
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Publication number: 20150154106Abstract: A data processing apparatus has a memory rename table for storing memory rename entries each identifying a mapping between a memory address of a location in memory and a mapped register of a plurality of registers. The mapped register is identified by a register number. In response to a store instruction, the store target memory address of the store instruction is mapped to a store destination register and so the data value is stored to the store destination register instead of memory. A memory rename entry is provided in the table to identify the mapping between the store target memory address and store destination target register. In response to a load instruction, if there is a hit in the memory rename table for the load target memory address then the loaded value can be read from the mapped register instead of memory.Type: ApplicationFiled: February 21, 2014Publication date: June 4, 2015Applicant: The Regents of the University of MichiganInventors: Joseph Michael PUSDESRIS, Yiping Kang, Andrea Pellegrini, Benjamin Allen Vandersloot, Trevor Nigel Mudge
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Patent number: 8868817Abstract: Interconnect circuitry 2 has a plurality of data source circuits 8 connected to respective input paths 4 and a plurality of data destination circuits 10 connected to respective output paths 6. Connection cells 12 provide selective connections between input paths 4 and output paths 6. Arbitration circuitry 26 provides adaptive priority arbitration between overlapping requests received at different input paths. Priority bits 16 within a matrix of priority bit 46 for each output path 10 are used to represent the priority relationships between different input paths which compete for access to that output path 10. Update operations are applied on a per row or per column basis within the matrix to implement update schemes such as least recently granted, most recently granted, round robin, reversal, swap, selective least recently granted, selective most recently granted etc.Type: GrantFiled: April 4, 2012Date of Patent: October 21, 2014Assignee: The Regents of the University of MichiganInventors: Sudhir Kumar Satpathy, David Theodore Blaauw, Dennis Michael Sylvester, Trevor Nigel Mudge
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Publication number: 20140181581Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.Type: ApplicationFiled: December 6, 2013Publication date: June 26, 2014Applicants: The Regents of the University of Michigan, ARM LimitedInventors: Krisztian FLAUTNER, Todd Michael AUSTIN, David Theodore BLAAUW, Trevor Nigel MUDGE, David BULL
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Patent number: 8650470Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.Type: GrantFiled: October 25, 2010Date of Patent: February 11, 2014Assignees: ARM Limited, The Regents of the University of MichiganInventors: Krisztian Flautner, Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge, David Bull
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Publication number: 20140019655Abstract: An interconnect 6 within an integrated circuit 2 provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).Type: ApplicationFiled: July 12, 2013Publication date: January 16, 2014Inventors: Supreet Jeloka, Sandunmalee Nilmini Abeyratne, Ronald George Dreslinski, Reetuparna Das, Trevor Nigel Mudge, David Theodore Blaauw
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Publication number: 20140013178Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.Type: ApplicationFiled: June 25, 2013Publication date: January 9, 2014Applicants: The Regents of the University of Michigan, ARM LimitedInventors: Krisztian FLAUTNER, Todd Michael AUSTIN, David Theodore BLAAUW, Trevor Nigel MUDGE, David BULL
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Publication number: 20130290679Abstract: A data processing system 2 is provided with branch prediction circuitry 20 for performing branch prediction operations. Next branch table circuitry 22 stores data identifying from a given branch instruction what will be the address of the next branch instruction to be encountered within the program flow. This next branch instruction address is supplied to the branch prediction circuitry 20 which uses it to form its prediction prior to that next branch instruction being identified as such by the instruction decoder 16. This permits branch prediction to commence earlier in the branch prediction circuitry 20 than would otherwise be the case.Type: ApplicationFiled: April 30, 2012Publication date: October 31, 2013Applicant: The Regents of the University of MichiganInventors: David Thomas Manville, Trevor Nigel Mudge