Patents by Inventor Trevor Nigel Mudge
Trevor Nigel Mudge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8549207Abstract: Crossbar circuitry has an array of data input and output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided which includes a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. In an arbitration mode of operation, the arbitration circuitry is operable to selectively modify the voltage on said plurality of bit lines in order to apply an adaptive priority scheme.Type: GrantFiled: November 18, 2010Date of Patent: October 1, 2013Assignee: The Regents of the University of MichiganInventors: Sudhir Kumar Satpathy, David Theodore Blaauw, Trevor Nigel Mudge, Dennis Michael Sylvester
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Patent number: 8407537Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.Type: GrantFiled: October 13, 2010Date of Patent: March 26, 2013Assignees: ARM Limited, The Regents of the University of MichiganInventors: Krisztian Flautner, Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge
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Patent number: 8346832Abstract: A circuit for generating a random output value is disclosed that comprises: a bistable circuit having two stable states in which a 0 or a 1 is output and having a balanced metastable state in which a floating value between 0 and 1 is output, said bistable circuit resolving from said metastable state to one of said stable states on being switched on, said state depending on a voltage level at a port on said bistable circuit; a voltage level control circuit for controlling a voltage level at said port on said bistable circuit; a time measuring circuit for measuring a switching time taken for said bistable circuit to switch from said metastable state to one of said stable states following switch on; and control logic for controlling said time measuring circuit, said voltage level control circuit and a switching off and on of said bistable circuit, said control logic being adapted to perform a following sequence: control said voltage level control circuit to set a predetermined voltage level at said port on saidType: GrantFiled: July 19, 2007Date of Patent: January 1, 2013Assignee: The Regents of the University of MichiganInventors: Trevor Nigel Mudge, David Theodore Blaauw, Carlos Alfonso Tokunaga
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Patent number: 8335122Abstract: A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it has a first memory cell group configured to operate in a first voltage domain and a second memory cell group configured to operate in a second voltage domain that is different from the first voltage domain. A corresponding data processing method is also provided.Type: GrantFiled: November 12, 2008Date of Patent: December 18, 2012Assignee: The Regents of the University of MichiganInventors: Ronald George Dreslinski, Jr., Gregory Kengho Chen, Trevor Nigel Mudge, David Theodore Blaauw, Dennis Sylvester
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Patent number: 8285936Abstract: A data processing apparatus 1 comprises data processing circuitry 2, a memory 8 for storing data and a cache memory 5 for storing cached data from the memory 8. The cache memory 5 is partitioned into cache segments 12 which may be individually placed in a power saving state by power supply circuitry 15 under control of power control circuitry 22. The number of segments which are active at any time may be dynamically adjusted in dependence upon operating requirements of the processor 2. An eviction selection mechanism 35 is provided to select evictable cached data for eviction from the cache. A cache compacting mechanism 40 is provided to evict evictable cached data from the cache and to store non-evictable cached data in fewer cache segments than were used to store the cached data prior to eviction of the evictable cached data.Type: GrantFiled: October 20, 2009Date of Patent: October 9, 2012Assignee: The Regents of the University of MichiganInventors: David Andrew Roberts, Trevor Nigel Mudge, Thomas Friedric Wenisch
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Patent number: 8255610Abstract: Crossbar circuitry has data input and output paths, and at each intersection between a data input and output path, a crossbar cell is provided. A transmission circuit is responsive to a stored routing value to couple a data input path to a selected data output path. Pre-selection circuitry cooperates with the pre-selection circuits of other crossbar cells on the same data output path to use the bit lines of the data output path to compare quality-of-service values associated with multiple asserted transmission requests and to determine a subset thereof which have a highest value of the quality-of-service values. Arbitration circuitry implements a predetermined priority scheme to choose from that subset of requests and to cause the configuration storage circuit of only one crossbar cell associated with the same data output path to have its routing value programmed to the first value, thereby resolving conflict between multiple asserted transmission requests.Type: GrantFiled: August 19, 2011Date of Patent: August 28, 2012Assignee: The Regents of the University of MichiganInventors: Sudhir Kumar Satpathy, David Theodore Blaauw, Trevor Nigel Mudge, Dennis Michael Sylvester
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Patent number: 8230152Abstract: Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection.Type: GrantFiled: July 14, 2009Date of Patent: July 24, 2012Assignee: The Regents of the University of MichiganInventors: Sudhir Kumar Satpathy, David Theodore Blaauw, Trevor Nigel Mudge, Dennis Michael Sylvester
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Patent number: 8230277Abstract: Data storage control circuitry for controlling storage and retrieval of data in a data store in which data is stored in data blocks. A group data store stores data by grouping together blocks that have at least one faulty bit into groups of at least two blocks. For each group of blocks at least one of the blocks has a non-faulty bit for each of the bit locations in the blocks. A selector data store stores indicators for each group indicating which bits of the blocks within a group are the non-faulty bits. When storing data to a data block within a group, the data is stored in each of the blocks within the group. When retrieving data from a data block within a group, the data is read from respective bits of the blocks within the group as indicated by the indicators.Type: GrantFiled: April 4, 2011Date of Patent: July 24, 2012Assignees: ARM Limited, The Regents of the University of MichiganInventors: Trevor Nigel Mudge, Ganesh Suryanarayan Dasika, David Andrew Roberts
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Patent number: 8185786Abstract: An integrated circuit includes a plurality of processing stages each including processing logic, a non-delayed signal-capture element, a delayed signal-capture element and a comparator. The non-delayed signal-capture element captures an output from the processing logic at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element also captures a value from the processing logic. An error detection circuit and error correction circuit detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator. The comparator compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.Type: GrantFiled: October 13, 2010Date of Patent: May 22, 2012Assignees: ARM Limited, The Regents of the University of MichiganInventors: Krisztian Flautner, Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge
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Patent number: 8145960Abstract: Data storage control circuitry for controlling storage and retrieval of data in a data store in which data is stored in data blocks. A group data store stores data by grouping together blocks that have at least one faulty bit into groups of at least two blocks. For each group of blocks at least one of the blocks has a non-faulty bit for each of the bit locations in the blocks. A selector data store stores indicators for each group indicating which bits of the blocks within a group are the non-faulty bits. When storing data to a data block within a group, the data is stored in each of the blocks within the group. When retrieving data from a data block within a group, the data is read from respective bits of the blocks within the group as indicated by the indicators.Type: GrantFiled: July 2, 2007Date of Patent: March 27, 2012Assignees: ARM Limited, The Regents of the University of MichiganInventors: Trevor Nigel Mudge, Ganesh Suryanarayan Dasika, David Andrew Roberts
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Publication number: 20120047310Abstract: Crossbar circuitry has data input and output paths, and at each intersection between a data input and output path, a crossbar cell is provided. A transmission circuit is responsive to a stored routing value to couple a data input path to a selected data output path. Pre-selection circuitry cooperates with the pre-selection circuits of other crossbar cells on the same data output path to use the bit lines of the data output path to compare quality-of-service values associated with multiple asserted transmission requests and to determine a subset thereof which have a highest value of the quality-of-service values. Arbitration circuitry implements a predetermined priority scheme to choose from that subset of requests and to cause the configuration storage circuit of only one crossbar cell associated with the same data output path to have its routing value programmed to the first value, thereby resolving conflict between multiple asserted transmission requests.Type: ApplicationFiled: August 19, 2011Publication date: February 23, 2012Applicant: The Regents of the University of MichiganInventors: Sudhir Kumar Satpathy, David Theodore Blaauw, Trevor Nigel Mudge, Dennis Michael Sylvester
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Patent number: 8108585Abstract: Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a storage circuit programmable to store a routing value, and a transmission circuit. In a transmission mode of operation the transmission circuit is responsive to the routing value indicating that the data input path should be coupled to the data output path to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. Control circuitry is used to issue control signals to the crossbar cells, and during a configuration mode of operation the control circuitry re-utilizes at least one of the data output paths to program the storage circuitry of one or more of the crossbar cells.Type: GrantFiled: February 13, 2009Date of Patent: January 31, 2012Assignee: The Regents of the Universtiy of MichiganInventors: Sudhir Kumar Satpathy, David Theodore Blaauw, Trevor Nigel Mudge, Dennis Michael Sylvester, Ronald George Dreslinski, Jr.
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Publication number: 20110185260Abstract: Data storage control circuitry for controlling storage and retrieval of data in a data store in which data is stored in data blocks. A group data store stores data by grouping together blocks that have at least one faulty bit into groups of at least two blocks. For each group of blocks at least one of the blocks has a non-faulty bit for each of the bit locations in the blocks. A selector data store stores indicators for each group indicating which bits of the blocks within a group are the non-faulty bits. When storing data to a data block within a group, the data is stored in each of the blocks within the group. When retrieving data from a data block within a group, the data is read from respective bits of the blocks within the group as indicated by the indicators.Type: ApplicationFiled: April 4, 2011Publication date: July 28, 2011Inventors: Trevor Nigel Mudge, Ganesh Suryanarayan Dasika, David Andrew Roberts
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Publication number: 20110138098Abstract: Crossbar circuitry has an array of data input and output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided which includes a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. In an arbitration mode of operation, the arbitration circuitry is operable to selectively modify the voltage on said plurality of bit lines in order to apply an adaptive priority scheme.Type: ApplicationFiled: November 18, 2010Publication date: June 9, 2011Applicant: The Regents of the University of MichiganInventors: Sudhir Kumar Satpathy, David Theodore Blaauw, Trevor Nigel Mudge, Dennis Michael Sylvester
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Publication number: 20110126051Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.Type: ApplicationFiled: October 13, 2010Publication date: May 26, 2011Inventors: Krisztian Flautner, Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge
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Publication number: 20110107166Abstract: An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.Type: ApplicationFiled: October 25, 2010Publication date: May 5, 2011Applicants: Arm Limited, The Regents of the University of MichganInventors: Krisztian Flautner, Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge, David Bull
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Publication number: 20110093654Abstract: A data processing apparatus 1 comprises data processing circuitry 2, a memory 8 for storing data and a cache memory 5 for storing cached data from the memory 8. The cache memory 5 is partitioned into cache segments 12 which may be individually placed in a power saving state by power supply circuitry 15 under control of power control circuitry 22. The number of segments which are active at any time may be dynamically adjusted in dependence upon operating requirements of the processor 2. An eviction selection mechanism 35 is provided to select evictable cached data for eviction from the cache. A cache compacting mechanism 40 is provided to evict evictable cached data from the cache and to store non-evictable cached data in fewer cache segments than were used to store the cached data prior to eviction of the evictable cached data.Type: ApplicationFiled: October 20, 2009Publication date: April 21, 2011Applicant: The regents of the University of MichiganInventors: David Andrew Roberts, Trevor Nigel Mudge, Thomas Friedric Wenisch
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Publication number: 20110093737Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.Type: ApplicationFiled: October 13, 2010Publication date: April 21, 2011Inventors: Krisztian Flautner, Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge
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Publication number: 20100211719Abstract: Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a storage circuit programmable to store a routing value, and a transmission circuit. In a transmission mode of operation the transmission circuit is responsive to the routing value indicating that the data input path should be coupled to the data output path to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. Control circuitry is used to issue control signals to the crossbar cells, and during a configuration mode of operation the control circuitry re-utilises at least one of the data output paths to program the storage circuitry of one or more of the crossbar cells.Type: ApplicationFiled: February 13, 2009Publication date: August 19, 2010Inventors: Sudhir Kumar SATPATHY, David Theodore BLAAUW, Trevor Nigel MUDGE, Dennis Michael SYLVESTER, Ronald George DRESLINKSKI, JR.
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Publication number: 20100211720Abstract: Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection.Type: ApplicationFiled: July 14, 2009Publication date: August 19, 2010Applicant: The Regents of the University of MichiganInventors: Sudhir Kumar Satpathy, David Theodore Blaauw, Trevor Nigel Mudge, Dennis Michael Sylvester