Patents by Inventor Trevor Nigel Mudge
Trevor Nigel Mudge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7701240Abstract: An integrated circuit 2 has a specified range of runtime-variable operating parameters. Data processing circuits 4 within the integrated circuit 2 have associated error detection and error repair mechanisms 6. When operating within a narrow typical-case range of runtime-variable operating parameters the data processing circuits 4 operate correctly and substantially without error. When operating outside of this typical-case range but inside the specified range of permitted values for the run-time variable operating parameters, then the error detection and error repair circuit 6 operate to repair the errors which occur.Type: GrantFiled: December 13, 2005Date of Patent: April 20, 2010Assignees: ARM Limited, The Regents of the University of MichiganInventors: Krisztian Flautner, David Michael Bull, Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge
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Patent number: 7650551Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 2, a non-delayed latch 4, a delayed latch 8 and a comparator 6. The non-delayed latch 4 captures an output from the processing logic 2 at a non-delayed capture time. At a later delayed capture time, the delayed latch 8 also captures a value from the processing logic 2. The comparator 6 compares these values and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock.Type: GrantFiled: August 16, 2007Date of Patent: January 19, 2010Assignees: ARM Limited, University of MichiganInventors: Krisztian Flautner, Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge
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Publication number: 20090138890Abstract: A hardware transactional memory 12, 14, 16, 18, 20 is provided within a multiprocessor 4, 6, 8, 10 system with coherency control and hardware transaction memory control circuitry 22 that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data 26, 28, 30. The conflict data characterises previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.Type: ApplicationFiled: November 20, 2008Publication date: May 28, 2009Applicant: ARM LIMITEDInventors: Geoffrey Blake, Trevor Nigel Mudge, Stuart David Biles, Nathan Yong Seng Chong, Emre Ozer, Ronald George Dreslinski
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Publication number: 20090138658Abstract: A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it has a first memory cell group configured to operate in a first voltage domain and a second memory cell group configured to operate in a second voltage domain that is different from the first voltage domain. A corresponding data processing method is also provided.Type: ApplicationFiled: November 12, 2008Publication date: May 28, 2009Applicant: The Regents of the University of MichiganInventors: Ronald George Dreslinski, JR., Gregory Kengho Chen, Trevor Nigel Mudge, David Theodore Blaauw, Dennis Sylvester
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Publication number: 20090133032Abstract: A hardware transactional memory 12, 14, 16, 18, 20 is provided within a multiprocessor 4, 6, 8, 10 system with coherency control and hardware transaction memory control circuitry 22 that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data 26, 28, 30. The conflict data characterises previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.Type: ApplicationFiled: April 24, 2008Publication date: May 21, 2009Inventors: Stuart David Biles, Geoffrey Blake, Trevor Nigel Mudge
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Patent number: 7512820Abstract: Performance level selection is carried out by calculating a plurality of performance requests using a plurality of performance request calculating algorithms, combining those different performance requests to form a global performance request and then selecting a performance level in dependence upon the global performance level request. The performance request calculating algorithms can be arranged in a hierarchy with their performance requests evaluated in a sequence starting from the least dominant position in the hierarchy and moving through to the most dominant position in the hierarchy. Commands may accompany each performance level request to specify how it should be combined with other performance level requests.Type: GrantFiled: September 13, 2006Date of Patent: March 31, 2009Assignees: ARM Limited, University of MichiganInventors: Krisztian Flautner, Trevor Nigel Mudge
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Publication number: 20080091755Abstract: A circuit for generating a random output value is disclosed that comprises: a bistable circuit having two stable states in which a 0 or a 1 is output and having a balanced metastable state in which a floating value between 0 and 1 is output, said bistable circuit resolving from said metastable state to one of said stable states on being switched on, said state depending on a voltage level at a port on said bistable circuit; a voltage level control circuit for controlling a voltage level at said port on said bistable circuit; a time measuring circuit for measuring a switching time taken for said bistable circuit to switch from said metastable state to one of said stable states following switch on; and control logic for controlling said time measuring circuit, said voltage level control circuit and a switching off and on of said bistable circuit, said control logic being adapted to perform a following sequence: control said voltage level control circuit to set a predetermined voltage level at said port on saidType: ApplicationFiled: July 19, 2007Publication date: April 17, 2008Inventors: Trevor Nigel Mudge, David Theodore Blaauw, Carlos Alfonso Tokunaga
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Systematic and random error detection and recovery within processing stages of an integrated circuit
Patent number: 7337356Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.Type: GrantFiled: July 23, 2004Date of Patent: February 26, 2008Assignees: ARM Limited, University of MichiganInventors: Trevor Nigel Mudge, Todd Michael Austin, David Theodore Blaauw, Krisztian Flautner -
Patent number: 7321942Abstract: A performance counter accumulates a value by periodically adding a variable increment value representing the amount of work performed. The increment value can be varied in dependence upon the processor clock frequency and may be adjusted under hardware and/or software control.Type: GrantFiled: October 20, 2003Date of Patent: January 22, 2008Assignees: ARM Limited, University of MichiganInventors: Krisztian Flautner, Trevor Nigel Mudge, David Walter Flynn
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Patent number: 7310755Abstract: An integrated circuit having a plurality of processing stages includes a low power mode controller operable to control the integrated circuit to switch between an operational mode and a standby mode. At least one of the processing stages has a non-delayed latch to capture a non-delayed value of an output signal from that processing stage and a delayed latch operable during the operational mode to capture a delayed value of the same signal. A difference between these two captured signals is indicative of the processing operation not being completed at the time the non-delayed signal was captured. The delayed latch is operable during the standby mode to retain the signal it captured whilst the non-delayed latch is powered down and loses its value. The delayed latch is formed to have a lower power consumption than the non-delayed latch.Type: GrantFiled: February 18, 2004Date of Patent: December 18, 2007Assignees: ARM Limited, University of MichiganInventors: Trevor Nigel Mudge, Todd Michael Austin, David Theodore Blaauw, Krisztian Flautner
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Patent number: 7278080Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 2, a non-delayed latch 4, a delayed latch 8 and a comparator 6. The non-delayed latch 4 captures an output from the processing logic 2 at a non-delayed capture time. At a later delayed capture time, the delayed latch 8 also captures a value from the processing logic 2. The comparator 6 compares these values and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock.Type: GrantFiled: March 20, 2003Date of Patent: October 2, 2007Assignees: ARM Limited, University of MichiganInventors: Krisztian Flautner, Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge
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Patent number: 7194385Abstract: A target processor performance level is calculated from a utilisation history of a processor in performance of a plurality of processing tasks. The method comprises calculating a task work value indicating processor utilisation in performing a given processing task within a predetermined task time-interval and calculating a target processor performance level in dependence upon the task work value.Type: GrantFiled: October 20, 2003Date of Patent: March 20, 2007Assignees: ARM Limited, University of MichiganInventors: Krisztian Flautner, Trevor Nigel Mudge
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Systematic and random error detection and recovery within processing stages of an integrated circuit
Patent number: 7162661Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.Type: GrantFiled: February 18, 2004Date of Patent: January 9, 2007Assignees: ARM Limited, University of MichiganInventors: Trevor Nigel Mudge, Todd Michael Austin, David Theodore Blaauw, Krisztian Flautner -
Patent number: 7131015Abstract: Performance level selection is carried out by calculating a plurality of performance requests using a plurality of performance request calculating algorithms, combining those different performance requests to form a global performance request and then selecting a performance level in dependence upon the global performance level request. The performance request calculating algorithms can be arranged in a hierarchy with their performance requests evaluated in a sequence starting from the least dominant position in the hierarchy and moving through to the most dominant position in the hierarchy. Commands may accompany each performance level request to specify how it should be combined with other performance level requests.Type: GrantFiled: October 20, 2003Date of Patent: October 31, 2006Assignees: ARM Limited, University of MichiganInventors: Krisztian Flautner, Trevor Nigel Mudge
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Patent number: 7072229Abstract: There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from said memory to generate a slow read result available after said fast read result has been output for further processing, said slow data reading mechanism being less prone to error in reading said data value than said fast data reading mechanism; a comparator operable to compare said fast read result and said slow read result to detect if said fast read result differs from said slow read result; and error repair logic operable if said comparator detects that said fast read result differs from said slow read result to suppress said further processing using said fast read result, to output said slow read result in place of said fast read result and to restart said further processing based upon said slow read result.Type: GrantFiled: June 13, 2005Date of Patent: July 4, 2006Assignees: ARM Limited, The Regents of the University of MichiganInventors: Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge, Dennis Michael Sylvester, Krisztian Flautner
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Patent number: 6944067Abstract: There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from said memory to generate a slow read result available after said fast read result has been output for further processing, said slow data reading mechanism being less prone to error in reading said data value than said fast data reading mechanism a comparator operable to compare said fast read result and said slow read result to detect if said fast read result differs from said slow read result; and error repair logic operable if said comparator detects that said, fast read result differs from said slow read result to suppress said further processing using said fast read result, to output said slow read result in place of said fast read result and to restart said further processing based upon said slow read result.Type: GrantFiled: February 18, 2004Date of Patent: September 13, 2005Assignee: ARM LimitedInventors: Trevor Nigel Mudge, Todd Michael Austin, David Theodore Blaauw, Dennis Michael Sylvester, Krisztian Flautner
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Systematic and random error detection and recovery within processing stages of an integrated circuit
Publication number: 20040243893Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.Type: ApplicationFiled: February 18, 2004Publication date: December 2, 2004Applicants: ARM Limited, University of MichiganInventors: Trevor Nigel Mudge, Todd Michael Austin, David Theodore Blaauw, Krisztian Flautner -
Publication number: 20040239397Abstract: There is provided an integrated circuit comprising:Type: ApplicationFiled: February 18, 2004Publication date: December 2, 2004Applicants: ARM LIMITED, University of MichiganInventors: Trevor Nigel Mudge, Todd Michael Austin, David Theodore Blaauw, Krisztian Flautner
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Publication number: 20040223386Abstract: There is provided a memory for storing data comprising:Type: ApplicationFiled: February 18, 2004Publication date: November 11, 2004Applicant: ARM LimitedInventors: Trevor Nigel Mudge, Todd Michael Austin, David Theodore Blaauw, Dennis Michael Sylvester, Krisztian Flautner
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Publication number: 20040199821Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 2, a non-delayed latch 4, a delayed latch 8 and a comparator 6. The non-delayed latch 4 captures an output from the processing logic 2 at a non-delayed capture time. At a later delayed capture time, the delayed latch 8 also captures a value from the processing logic 2. The comparator 6 compares these values and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock.Type: ApplicationFiled: March 20, 2003Publication date: October 7, 2004Inventors: Krisztian Flautner, Todd Michael Austin, David Theodore Blaauw, Trevor Nigel Mudge