Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: A convertible cart for restaurants for carrying stacked chairs when a convertible section of the cart is in a first position. The cart is adapted for carrying a trough of dishes, food, and other dining items, food when the convertible section is in a second position. The cart features a convertible preferably tubular U-shaped section spaced up from the base that pivots from the vertical to the horizontal. The U-shaped section carries a pivotable support arm engageable to either the cart handle when the U-shaped section is in the first vertical position, or engageable to the cart base when the convertible section is in the second horizontal position. A trough or flat board can rest on or be engaged with the U-shaped section when in the horizontal position for carrying utensils, food, waste, condiments or the like, as utilized by a restaurant or bar.

Abstract: An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

Abstract: A system and method for playing back data segments stored in one or more locations and managed by one or more playback servers. In a preferred embodiment the system and method receive data describing data segments to be played back; transmit notifications to the playback servers to prepare for playback; and transmit playback requests to the playback servers. The system and method are also capable of playing back the segments in a specified order and such that gaps between the segments are minimized. Additionally, a graphical display can be provided to display the status of the segments being played back.

Abstract: An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

Abstract: A multi-function exercise apparatus includes a frame, left and right pedal guides, left and right foot pedals and left and right handles. The left and right pedal guides are constrained to pivot back and forth reciprocally, and the left and right foot pedals are constrained to slide reciprocally along the pedal guides. Additionally, the apparatus may include resistance subsystems configured to selectively apply a resistance force against the pivot motion of the pedal guides and the radial motion of the foot pedals along the length of the pedal guides. The left and right handles are coupled to the left and right pedal guides for upper body exercise.

Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.

Abstract: A convertible cart for restaurants for carrying stacked chairs when a convertible section of the cart is in a first position. The cart is adapted for carrying a trough of dishes, food, and other dining items, food when the convertible section is in a second position. The cart features a convertible preferably tubular U-shaped section spaced up from the base that pivots from the vertical to the horizontal. The U-shaped section carries a pivotable support arm engageable to either the cart handle when the U-shaped section is in the first vertical position, or engageable to the cart base when the convertible section is in the second horizontal position. A trough or flat board can rest on or be engaged with the U-shaped section when in the horizontal position for carrying utensils, food, waste, condiments or the like, as utilized by a restaurant or bar.

Abstract: First and second connector housings (20, 26) each hold a corresponding set (22, 30) of numerous fibers, that are coupled when their tips (40, 42) abut, in a low-cost and rugged arrangement. The housings are identical and each has numerous bores (50, 52) extending to a mating face (34, 36). Each fiber is fixed in position in one of the bores, by potting material (64). The diameters of the bores are only slightly greater than the diameters of the fibers, so the potting material helps center the fiber in the end of the bore that lies adjacent to the mating face.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: An optical fiber connector (12) has a terminus (34) lying in a housing passage (44) and biased forwardly by a spring (80), which enables removal of the terminus while the spring remains in the passage, in a compact arrangement. The terminus body has a groove (112) that forms a rearwardly-facing shoulder (120). A retainer (142) includes a clip (102) with tines (110) that engage the shoulder to push the terminus forwardly, the clip being pushed forwardly by a front end (92) of the spring. The retainer includes a sleeve member (100) which is slideable in the terminus passage and has a rear end (94) that abuts the front end of the spring to push the sleeve forwardly, the spring having a forwardly-facing shoulder (104) that abuts the rear end of the clip to push it forwardly. Each of two mating connectors (12, 14) has a spring that biases its terminus toward the other terminus to enable installation of a replacement terminus.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: A computer system comprising a microprocessor architecture capable of supporting multiple processors comprising a memory array unit (MAU), an MAU system bus comprising data, address and control signal buses, an I/O bus comprising data, address and control signal buses, a plurality of I/O devices and a plurality of microprocessors. Data transfers between data and instruction caches and I/O devices and a memory and other I/O devices are handled using a switch network port data and instruction cache and I/O interface circuits. Access to the memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes. A test and set bypass circuit is provided for preventing a loss of memory bandwidth due to spin-locking. A content addressable memory (CAM) is used to store the address of the semaphore and is checked by devices attempting to access the memory to determine whether the memory is available before an address is placed on the memory bus.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: The invention provides a method and apparatus for controlling dampers in a suspension system of a vehicle body. A heave velocity of a vehicle body is derived from sensed dynamic variables of the vehicle body. A slew rate limit for a damping control command is derived in response to the heave velocity of the vehicle body. The damping control command for at least one dampers is generated in accordance with the slew rate limit.