Patents by Inventor Trong Nguyen

Trong Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6954847
    Abstract: A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions.
    Type: Grant
    Filed: February 4, 2002
    Date of Patent: October 11, 2005
    Assignee: Transmeta Corporation
    Inventors: Brett Coon, Yoshiyuki Miyayama, Le Trong Nguyen, Johannes Wang
  • Patent number: 6948052
    Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: September 20, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
  • Patent number: 6941447
    Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: September 6, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Le-Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
  • Patent number: 6934829
    Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: August 23, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
  • Patent number: 6915412
    Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: July 5, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
  • Patent number: 6910710
    Abstract: A convertible cart for restaurants for carrying stacked chairs when a convertible section of the cart is in a first position. The cart is adapted for carrying a trough of dishes, food, and other dining items, food when the convertible section is in a second position. The cart features a convertible preferably tubular U-shaped section spaced up from the base that pivots from the vertical to the horizontal. The U-shaped section carries a pivotable support arm engageable to either the cart handle when the U-shaped section is in the first vertical position, or engageable to the cart base when the convertible section is in the second horizontal position. A trough or flat board can rest on or be engaged with the U-shaped section when in the horizontal position for carrying utensils, food, waste, condiments or the like, as utilized by a restaurant or bar.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: June 28, 2005
    Inventor: Trong Nguyen
  • Publication number: 20040243961
    Abstract: An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.
    Type: Application
    Filed: July 8, 2004
    Publication date: December 2, 2004
    Applicant: Seiko Epson Corporation
    Inventors: Kevin Ray Iadonato, Le Trong Nguyen
  • Patent number: 6785369
    Abstract: A system and method for playing back data segments stored in one or more locations and managed by one or more playback servers. In a preferred embodiment the system and method receive data describing data segments to be played back; transmit notifications to the playback servers to prepare for playback; and transmit playback requests to the playback servers. The system and method are also capable of playing back the segments in a specified order and such that gaps between the segments are minimized. Additionally, a graphical display can be provided to display the status of the segments being played back.
    Type: Grant
    Filed: June 8, 2001
    Date of Patent: August 31, 2004
    Assignee: Dictaphone Corporation
    Inventors: David A. Diamond, David A. Glowny, Trong Nguyen, Phil Min Ni, John E. Richter
  • Patent number: 6782521
    Abstract: An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: August 24, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Kevin R. Iadonato, Le Trong Nguyen
  • Patent number: 6761665
    Abstract: A multi-function exercise apparatus includes a frame, left and right pedal guides, left and right foot pedals and left and right handles. The left and right pedal guides are constrained to pivot back and forth reciprocally, and the left and right foot pedals are constrained to slide reciprocally along the pedal guides. Additionally, the apparatus may include resistance subsystems configured to selectively apply a resistance force against the pivot motion of the pedal guides and the radial motion of the foot pedals along the length of the pedal guides. The left and right handles are coupled to the left and right pedal guides for upper body exercise.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: July 13, 2004
    Inventor: Hieu Trong Nguyen
  • Publication number: 20040128487
    Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.
    Type: Application
    Filed: November 17, 2003
    Publication date: July 1, 2004
    Applicant: Seiko Epson Corporation
    Inventors: Cheryl Senter Brashears, Johannes Wang, Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
  • Publication number: 20040108689
    Abstract: A convertible cart for restaurants for carrying stacked chairs when a convertible section of the cart is in a first position. The cart is adapted for carrying a trough of dishes, food, and other dining items, food when the convertible section is in a second position. The cart features a convertible preferably tubular U-shaped section spaced up from the base that pivots from the vertical to the horizontal. The U-shaped section carries a pivotable support arm engageable to either the cart handle when the U-shaped section is in the first vertical position, or engageable to the cart base when the convertible section is in the second horizontal position. A trough or flat board can rest on or be engaged with the U-shaped section when in the horizontal position for carrying utensils, food, waste, condiments or the like, as utilized by a restaurant or bar.
    Type: Application
    Filed: December 9, 2002
    Publication date: June 10, 2004
    Inventor: Trong Nguyen
  • Patent number: 6746159
    Abstract: First and second connector housings (20, 26) each hold a corresponding set (22, 30) of numerous fibers, that are coupled when their tips (40, 42) abut, in a low-cost and rugged arrangement. The housings are identical and each has numerous bores (50, 52) extending to a mating face (34, 36). Each fiber is fixed in position in one of the bores, by potting material (64). The diameters of the bores are only slightly greater than the diameters of the fibers, so the potting material helps center the fiber in the end of the bore that lies adjacent to the mating face.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: June 8, 2004
    Assignee: ITT Manufacturing Enterprises, Inc.
    Inventors: Peter Joseph Hyzin, Can Trong Nguyen, James Edward Novacoski
  • Publication number: 20040093482
    Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.
    Type: Application
    Filed: November 5, 2003
    Publication date: May 13, 2004
    Applicant: Seiko Epson Corporation
    Inventors: Le-Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
  • Publication number: 20040093485
    Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.
    Type: Application
    Filed: November 5, 2003
    Publication date: May 13, 2004
    Applicant: Seiko Epson Corporation
    Inventors: Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
  • Publication number: 20040093483
    Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.
    Type: Application
    Filed: October 31, 2003
    Publication date: May 13, 2004
    Applicant: Seiko Epson Corporation
    Inventors: Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
  • Patent number: 6722789
    Abstract: An optical fiber connector (12) has a terminus (34) lying in a housing passage (44) and biased forwardly by a spring (80), which enables removal of the terminus while the spring remains in the passage, in a compact arrangement. The terminus body has a groove (112) that forms a rearwardly-facing shoulder (120). A retainer (142) includes a clip (102) with tines (110) that engage the shoulder to push the terminus forwardly, the clip being pushed forwardly by a front end (92) of the spring. The retainer includes a sleeve member (100) which is slideable in the terminus passage and has a rear end (94) that abuts the front end of the spring to push the sleeve forwardly, the spring having a forwardly-facing shoulder (104) that abuts the rear end of the clip to push it forwardly. Each of two mating connectors (12, 14) has a spring that biases its terminus toward the other terminus to enable installation of a replacement terminus.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: April 20, 2004
    Assignee: ITT Manufacturing Enterprises, Inc.
    Inventors: Peter Joseph Hyzin, James Edward Novacoski, Can Trong Nguyen
  • Publication number: 20040054872
    Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.
    Type: Application
    Filed: September 12, 2003
    Publication date: March 18, 2004
    Applicant: Seiko Epson Corporation
    Inventors: Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te-Li Lau, Sze-Shun Wang, Quang H. Trang
  • Patent number: D506354
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: June 21, 2005
    Inventor: Trong Nguyen
  • Patent number: D494813
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: August 24, 2004
    Inventor: Trong Nguyen