Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one or more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.

Abstract: A retainer (60) at the rear of each passage (14) that holds an optical fiber terminus (30), abuts the rear end (62) of a spring to normally retain the terminus while allowing its removal, with the retainer being rugged, easily manipulated, and of small diameter to allow numerous passages to lie close together. Each retainer has a primarily cylindrical outer surface (74) but with a pair of projections (80, 82). The rear portion of the passage has a first part (90) through which the retainer can be slid forwardly while the retainer is in an initial rotational orientation. A third passage part (94) receives the retainer and allows it to be turned from the initial orientation (60A) to a lock rotational orientation (60B). A second passage part (92) that lies between the first and third passage parts, allows the projections to move rearwardly into recesses (112) that prevent rotation of the retainer and that have forwardly-facing shoulders (114) that abut the retainer to limit its rearward movement.

Abstract: A method, system and computer readable medium storing a computer program is provided for independent control of a variable force damper system. The variable force damper system can be applied to control a vehicle suspension system. The system provides individual wheel control independent of vehicle body forces. In operation, at least one relative velocity signal and at least one body demand force is received. At least one body damper command is determined based on the body demand force. At least one wheel motion indicating parameter is determined based on the relative velocity signal. At least one wheel damper command is determined based on the wheel motion indicating parameter and a damper command is determined based on the larger of the body damper command and the wheel damper command.

Abstract: An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

Abstract: A data processing unit is disclosed with a register file having a plurality of registers. A memory having a plurality of n-bit input/output ports, and a coupling unit for coupling the memory with the register file, a memory address and select unit for addressing the memory banks are provided. The coupling unit comprises a bus having a bus width of at least 2n-bits forming at least a first and second sub-bus, first couplers for coupling each memory bank or the register file selectively with one of the sub-busses, and second couplers for coupling the register file or the memory banks with the bus.

Abstract: A multi-function exercise apparatus includes a frame, left and right pedal guides, left and right foot pedals and left and right handles. The left and right pedal guides are constrained to pivot back and forth reciprocally, and the left and right foot pedals are constrained to slide reciprocally along the pedal guides. Additionally, the apparatus may include resistance subsystems configured to selectively apply a resistance force against the pivot motion of the pedal guides and the radial motion of the foot pedals along the length of the pedal guides. The left and right handles are coupled to the left and right pedal guides for upper body exercise.

Abstract: A method and apparatus allowing two independent arbiters which do not directly talk to one another to function on a common system bus, allowing efficient operation of a master controller, and virtually endless capability to add peripherals to the common system bus without problems or major modifications commonly associated with additional arbitration overhead. A master controller sets time slot parameters for an external, subordinate arbiter as often as desired. Based on the time slot parameter information, the subordinate arbiter functions on an electrically separated portion of the common system bus during all times but for a time slot associated with communication of the super arbiter over the entire common system bus. During this time, a tri-state buffer element allows communication between portions of the common system bus.

Abstract: An optical fiber terminus body has a helical spring (32) trapped between front and rear shoulders, with the rear shoulder formed by a thin flange (64) that facilitates mounting of the spring on a one-piece body (40). The thin flange has front and rear surfaces that are angled by no more than about 30° from a radial direction, and the base of the flange has an axial length substantially no greater than the radial length of the flange, to facilitate installation of the spring by turning the spring to thread it past the flange.

Abstract: To achieve high performance at low cost, an integrated digital signal processor uses an architecture which includes both a general purpose processor and a vector processor. The integrated digital signal processor also includes a cache subsystem, a first bus and a second bus. The cache subsystem provides caching and data routing for the processors and buses. Multiple simultaneous communication paths can be used in the cache subsystem for the processors and buses. Furthermore, simultaneous reads and writes are supported to a cache memory in the cache subsystem.

Abstract: A data processing unit is disclosed with a register file having a plurality of registers. A memory having a plurality of n-bit input/output ports, and a coupling unit for coupling the memory with the register file, a memory address and select unit for addressing the memory banks are provided. The coupling unit comprises a bus having a bus width of at least 2n-bits forming at least a first and second sub-bus, first couplers for coupling each memory bank or the register file selectively with one of the sub-busses, and second couplers for coupling the register file or the memory banks with the bus.

Abstract: A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more complex microprocessor instructions requiring multiple cycles by sharing single-cycle operations, thereby reducing both costs and size of the microprocessor. One embodiment handles 288-bit data widths using 36-bit data path slices. Another embodiment executes integer multiply and multiply-and-accumulate and floating point add/subtract and multiply operations using single-cycle arithmetic logic units. Other embodiments support 8-bit, 9-bit, 16-bit, and 32-bit integer data types and 32-bit floating data types.

Abstract: An optical fiber connector is provided with a frame mount (182) having a passage (200) and a terminus (164) which extends through the passage to position an optical fiber (72) that extends through bores in the terminus, which enables the adjustment of terminus position for optimal coupling of the fiber tip (20) to the tip (22) of a fiber of a mating connector. The terminus has a pair of projections (220, 222) and the walls of the passage have a plurality of recesses to fix the rotational position of the terminus at any of a plurality of rotational positions. The terminus is accurately oriented so its axis extends in a desired direction, by forming a largely forwardly-facing conical surface (214) in the terminus and a corresponding rearwardly-facing conical surface (204) in the walls of the passage, the conical surfaces serving to accurately position the terminus.

Abstract: An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparator blocks in the rows. Tag assignment logic blocks are coupled to the data dependency comparator blocks to receive dependency information. The tag assignment logic blocks are positioned in one or more of the layout regions so as to be integrated with the data dependency comparator blocks to conserve area on the semiconductor chip and to spatially define a channel in and substantially orthogonal to one or more of the rows. Register file port multiplexer blocks are coupled to output lines of the tag assignment logic block adjacent to the orthogonal channel to receive tag information and to pass the tag information to address ports of a register file.

Abstract: A computer system comprising a microprocessor architecture capable of supporting multiple processors comprising a memory array unit (MAU), an MAU system bus comprising data, address and control signal buses, an I/O bus comprising data, address and control signal buses, a plurality of I/O devices and a plurality of microprocessors. Data transfers between data and instruction caches and I/O devices and a memory and other I/O devices are handled using a switch network port data and instruction cache and I/O interface circuits. Access to the memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes. A test and set bypass circuit is provided for preventing a loss of memory bandwidth due to spin-locking. A content addressable memory (CAM) is used to store the address of the semaphore and is checked by devices attempting to access the memory to determine whether the memory is available before an address is placed on the memory bus.

Abstract: An architecture is disclosed allowing a server to communicate bidirectionally with a gateway over a first communication link, over which service requests are initiated by the server. In response to a transaction received from a host legacy system at the gateway, the gateway parses one or more transaction response values from the host message, maps the one or more transaction response values to a canonical response code, and stores the canonical response code in a transaction log. According to a broad aspect of a preferred embodiment of the invention, communication networks that employ transactions between applications must effectively manage transactions that flow over the network. In addition, networking systems must also detect counterfeit transactions, especially, when the networking systems are utilized for financial transactions. An active, on-line database is utilized as a transaction log to track original requests, valid retrys and detect fradulant transactions.

Abstract: A system and method for playing back data segments stored in one or more locations and managed by one or more playback servers. In a preferred embodiment the system and method receive data describing data segments to be played back; transmit notifications to the playback servers to prepare for playback; and transmit playback requests to the playback servers. The system and method are also capable of playing back the segments in a specified order and such that gaps between the segments are minimized. Additionally, a graphical display can be provided to display the status of the segments being played back.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.