Abstract: One embodiment of a hydraulic system for a machine has a first hydraulic circuit including a first pump coupled to a first hydraulic actuator configured to move a first implement of the machine. A second hydraulic circuit includes a second pump coupled to a second hydraulic actuator configured to move a second implement. An electric motor mechanically couples to the first pump and to the second pump. An operator interface receives input from an operator requesting movement of the first and second implements. A controller communicatively coupled to the electric motor and to the operator interface determines, based on the requested movement of the first and second implements respectively, first and second flow allocations respectively for the first and second pumps and determines respective target displacements for the first and second pumps.

Abstract: Provided are a computer program product, system, and method for determining a frequency at which to execute trap code in an execution path of a process executing a program to generate a trap address range to detect potential malicious code. Trap code is executed in response to processing a specified type of command in application code to allocate a trap address range used to detect potentially malicious code. A determination is whether to modify a frequency of executing the trap code in response to processing a specified type of command. The frequency of executing the trap code is modified in response to processing the specified type of command in response to determining to determining to modify the frequency of executing the trap code.

Abstract: In one embodiment, storage drive dependent track removal processing logic performs destage tasks for tracks cached in a cache as a function of whether the storage drive is classified as a fast class or as slow class of storage drives, for example. In one embodiment, a destage task configured for a slow class storage drive, transfers an entry for a track selected for destaging from a main cache list to a wait cache list to await destaging to the slow class drive. A destage task configured for a fast class storage drive allows the cache list entry for the selected track to remain on the main cache list while the selected track is being destaged to the fast class storage drive, thereby bypassing the transfer of the entry to a wait cache list. Other features and aspects may be realized, depending upon the particular application.

Abstract: A plurality of processing entities in which a plurality of tasks are executed are maintained. Memory access patterns are determined for each of the plurality of tasks by dividing a memory associated with the plurality of processing entities into a plurality of memory regions, and for each of the plurality of tasks, determining how many memory accesses take place in each of the memory regions, by incrementing a counter associated with each memory region in response to a memory access. Each of the plurality of tasks are allocated among the plurality of processing entities, based on the determined memory access patterns for each of the plurality of tasks.

Abstract: A method is disclosed to identify a port that is associated with a faulty cable. In one embodiment, such a method identifies a cable to replace. The cable provides a path between a first port, residing on a first component, and a second port, residing on a second component. The method further identifies whether an alternative path, bypassing the first cable, exists between the first component and the second component. In the event the alternative path exists, the method sends, over the alternative path, from the first component to the second component, a command to activate an indicator on the second port. This command is received and executed by the second component to activate the indicator. A corresponding apparatus and computer program product are also disclosed.

Abstract: A first non-volatile dual in-line memory module (NVDIMM) of a first server and a second NVDIMM of a second server are armed during initial program load in a dual-server based storage system to configure the first NVDIMM and the second NVDIMM to retain data on power loss. Prior to initiating a safe data commit scan to destage modified data from the first server to a secondary storage, a determination is made as to whether the first NVDIMM is armed. In response to determining that the first NVDIMM is not armed, a failover is initiated to the second server.

Abstract: Provided are a computer program product, system, and method for determining an optimum number of threads to make available per core in a multi-core processor complex to execute tasks. A determination is made of a first processing measurement based on threads executing on the cores of the processor chip, wherein each core includes circuitry to independently execute a plurality of threads. A determination is made of a number of threads to execute on the cores based on the first processing measurement. A determination is made of a second processing measurement based on the threads executing on the cores of the processor chip. A determination is made of an adjustment to the determined number of threads to execute based on the second processing measurement resulting in an adjusted number of threads. The adjusted number of threads on the cores is utilized to execute instructions.

Abstract: A plurality of central processing units (CPUs) are allocated as a set of dedicated CPUs for processing tasks of an input/output (I/O) resource. In response to determining that a CPU utilization for the set of dedicated CPUs is less than a first predetermined threshold, at least one CPU of the set of dedicated CPUs is configured as a reserved CPU to execute tasks for one or more entities other than the I/O resource. In response to determining that a CPU utilization for the set of dedicated CPUs is greater than a second predetermined threshold, the reserved CPU is configured as a dedicated CPU to process tasks for the I/O resource.

Abstract: A method for dispatching tasks on processor cores based on memory access efficiency is disclosed. The method identifies a task and a memory area to be accessed by the task. The method may use one or more of a compiler, code knowledge, and run-time statistics to identify the memory area that is accessed by the task. The method identifies multiple processor cores that are candidates to execute the task and identifies a particular processor core from the multiple processor cores that provides most efficient access to the memory area. The method dispatches the task to execute on the particular processor core that is deemed most efficient. A corresponding system and computer program product are also disclosed.

Abstract: A plurality of processing entities are maintained. A plurality of task control block (TCB) groups are generated, wherein each of the plurality of TCB groups are restricted to one or more different processing entities of the plurality of processing entities. A TCB is assigned to one of the plurality of TCB groups, at TCB creation time.

Abstract: In one aspect of multi-mode address mapping management in accordance with the present disclosure, mapping and unmapping operations may be conducted in one of multiple address mapping management modes to both improve overall system performance and maintain data integrity. In one embodiment, a first address mapping management mode such as a rigorous mode, for example, confirms completion of an unmapping of an address mapped data unit buffer before a re-mapping is permitted. Mapping and unmapping operations may be switched to a performance mode in which unmap completion confirmation is bypassed to improve performance. In one embodiment, address mapping management modes may be switched in real time as a function of monitored operating conditions. Other aspects and advantages are provided, depending upon the particular application.

Abstract: In one aspect of multi-mode address mapping management in accordance with the present disclosure, mapping and unmapping operations may be conducted in one of multiple address mapping management modes to both improve overall system performance and maintain data integrity. In one embodiment, a first address mapping management mode such as a rigorous mode, for example, confirms completion of an unmapping of an address mapped data unit buffer before a re-mapping is permitted. Mapping and unmapping operations may be switched to a performance mode in which unmap completion confirmation is bypassed to improve performance. In one embodiment, address mapping management modes may be switched in real time as a function of monitored operating conditions. Other aspects and advantages are provided, depending upon the particular application.

Abstract: A background process is configured to periodically scrub a boot storage of a storage controller to ensure operational correctness of the boot storage. One or more foreground processes store a system configuration data of the storage controller in the boot storage of the storage controller. The background process and the one or more foreground processes are executed to meet predetermined performance requirements for the background process and the one or more foreground processes.

Abstract: A plurality of dispatch queues corresponding to a plurality of processing entities are maintained, wherein each dispatch queue includes one or more task control blocks or is empty, and wherein an ordered list of dispatch queues is maintained for each processing entity of the plurality of processing entities. A state for each of the plurality of dispatch queues is determined and the determined state is compared to a desired state for the plurality of dispatch queues. A task control block is moved from one dispatch queue to another dispatch queue, in response to the comparing of the determined state to the desired state for the plurality of dispatch queues.

Abstract: A method for dispatching tasks on processor cores based on memory access efficiency is disclosed. The method identifies a task and a memory area to be accessed by the task. The method may use one or more of a compiler, code knowledge, and run-time statistics to identify the memory area that is accessed by the task. The method identifies multiple processor cores that are candidates to execute the task and identifies a particular processor core from the multiple processor cores that provides most efficient access to the memory area. The method dispatches the task to execute on the particular processor core that is deemed most efficient. A corresponding system and computer program product are also disclosed.

Abstract: Provided are a computer program product, system, and method for selecting resources to make available in local queues for processors to use. Each processor of a plurality of processors maintains a queue of resources for the processor to use when needed for processor operations. One of processors is selected. The selected processor accesses at least one available resource and includes the accessed at least one resource in the queue of the selected processor.

Abstract: Provided are a computer program product, system, and method for determining cores to assign to cache hostile tasks. A computer system has a plurality of cores. Each core is comprised of a plurality of processing units and at least one cache memory shared by the processing units on the core to cache data from a memory. A task is processed to determine one of the cores on which to dispatch the task. A determination is made as to whether the processed task is classified as cache hostile. A task is classified as cache hostile when the task accesses more than a threshold number of memory address ranges in the memory. The processed task is dispatched to at least one of the cores assigned to process cache hostile tasks.

Abstract: A computer-implemented method, according to one embodiment, includes: in response to experiencing a power loss event, resupplying power to NVRAM which includes a write cache. In response to detecting that the NVRAM has experienced a failure event, the NVRAM is temporarily guarded from further use. Moreover, a portion of volatile memory is allocated to serve as a temporary write cache. The allocated portion of volatile memory is also cleared. A determination is made as to whether data is present in the write cache in the NVRAM, and in response to determining that data is present in the write cache, one or more volumes in memory which correspond to the data present in the write cache in the NVRAM are marked as having experienced data loss. Furthermore, a warning is sent which indicates that data loss has been experienced by the one or more marked volumes in the memory.

Abstract: Provided are a computer program product, system, and method for monitoring correctable errors on a bus interface to determine whether to redirect traffic to another bus interface. A processing unit sends Input/Output (I/O) requests from a host to a storage over a first bus interface to a first device adaptor, wherein the first device adaptor provides a first connection to the storage. A determination is made as to whether a number of correctable errors on the first bus interface exceeds an error threshold. The correctable errors are detected and corrected in the first bus interface by hardware of the first bus interface. In response to determining that the number of correctable errors on the first bus interface exceeds the error threshold, at least a portion of I/O requests are redirected to use a second bus interface to connect to a second device adaptor providing a second connection to the storage.

Abstract: Provided are a computer program product, system, and method for determining a frequency at which to execute trap code in an execution path of a process executing a program to generate a trap address range to detect potential malicious code. Trap code is executed in response to processing a specified type of command in application code to allocate a trap address range used to detect potentially malicious code. A determination is whether to modify a frequency of executing the trap code in response to processing a specified type of command. The frequency of executing the trap code is modified in response to processing the specified type of command in response to determining to determining to modify the frequency of executing the trap code.