Abstract: Provided are a computer program product, system, and method for selecting resources to make available in local queues for processors to use. Each processor of a plurality of processors maintains a queue of resources for the processor to use when needed for processor operations. One of processors is selected. The selected processor accesses at least one available resource and includes the accessed at least one resource in the queue of the selected processor.

Abstract: A plurality of processing entities are maintained. A plurality of task control block (TCB) groups are generated, wherein each of the plurality of TCB groups are restricted to one or more different processing entities of the plurality of processing entities. A TCB is assigned to one of the plurality of TCB groups, at TCB creation time.

Abstract: Provided are a computer program product, system, and method for determining an optimum number of threads to make available per core in a multi-core processor complex to execute tasks. A determination is made of a first processing measurement based on threads executing on the cores of the processor chip, wherein each core includes circuitry to independently execute a plurality of threads. A determination is made of a number of threads to execute on the cores based on the first processing measurement. A determination is made of a second processing measurement based on the threads executing on the cores of the processor chip. A determination is made of an adjustment to the determined number of threads to execute based on the second processing measurement resulting in an adjusted number of threads. The adjusted number of threads on the cores is utilized to execute instructions.

Abstract: In one embodiment, storage drive dependent track removal processing logic performs destage tasks for tracks cached in a cache as a function of whether the storage drive is classified as a fast class or as slow class of storage drives, for example. In one embodiment, a destage task configured for a slow class storage drive, transfers an entry for a track selected for destaging from a main cache list to a wait cache list to await destaging to the slow class drive. A destage task configured for a fast class storage drive allows the cache list entry for the selected track to remain on the main cache list while the selected track is being destaged to the fast class storage drive, thereby bypassing the transfer of the entry to a wait cache list. Other features and aspects may be realized, depending upon the particular application.

Abstract: In one embodiment, performance-based multi-mode task dispatching for high temperature avoidance in accordance with the present description, includes selecting processor cores as available to receive a dispatched task. Tasks are dispatched to a set of available processor cores for processing in a performance-based dispatching mode. If monitored temperature rises above a threshold temperature value, task dispatching logic switches to a thermal-based dispatching mode. If a monitored temperature falls below another threshold temperature value, dispatching logic switches back to the performance-based dispatching mode. If a monitored temperature of an individual processor core rises above a threshold temperature value, the processor core is redesignated as unavailable to receive a dispatched task. If the temperature of an individual processor core falls below another threshold temperature value, the processor core is redesignated as available to receive a dispatched task.

Abstract: Provided are a computer program product, system, and method for determining a frequency at which to execute trap code in an execution path of a process executing a program to generate a trap address range to detect potential malicious code. Trap code is executed in response to processing a specified type of command in application code to allocate a trap address range used to detect potentially malicious code. A determination is whether to modify a frequency of executing the trap code in response to processing a specified type of command. The frequency of executing the trap code is modified in response to processing the specified type of command in response to determining to determining to modify the frequency of executing the trap code.

Abstract: A plurality of ordered lists of dispatch queues corresponding to a plurality of processing entities are maintained, wherein each dispatch queue includes one or more task control blocks or is empty. A determination is made as to whether a primary dispatch queue of a processing entity is empty in an ordered list of dispatch queues for the processing entity. In response to determining that the primary dispatch queue of the processing entity is empty, a task control block is selected for processing by the processing entity from another dispatch queue of the ordered list of dispatch queues for the processing entity, wherein the another dispatch queue from which the task control block is selected meets a threshold criteria for the processing entity.

Abstract: Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.

Abstract: Provided are techniques for detecting a type of storage adapter connected to an Input/Output (I/O) bay and miscabling of a microbay housing the storage adapter. Under control of an Input/Ouput (I/O) bay, cable sidebands are driven high for a predetermined period of time. It is determined whether a cable sidebands response has been detected that indicates that the cable sidebands have been driven low. In response to determining that the cable sidebands response has been detected, it is determined that the I/O bay is connected to a first storage adapter supporting a first protocol for the cable sidebands. In response to determining that the cable sidebands response has not been detected, it is determined that the I/O bay is connected to a second storage adapter supporting a second protocol for the cable sidebands. Moreover, I/O bay and port numbers stored by the microbay are used to determine miscabling.

Abstract: In one embodiment, storage drive dependent track removal processing logic performs destage tasks for tracks cached in a cache as a function of whether the storage drive is classified as a fast class or as slow class of storage drives, for example. In one embodiment, a destage task configured for a slow class storage drive, transfers an entry for a track selected for destaging from a main cache list to a wait cache list to await destaging to the slow class drive. A destage task configured for a fast class storage drive allows the cache list entry for the selected track to remain on the main cache list while the selected track is being destaged to the fast class storage drive, thereby bypassing the transfer of the entry to a wait cache list. Other features and aspects may be realized, depending upon the particular application.

Abstract: A battery packaging arrangement. The battery packaging arrangement includes a first base configured to be fixedly coupled to a frame of a vehicle, a second base moveable with respect to the first base, and a plurality of cooling columns inter-disposed between the first base and the second base. Each of the plurality of cooling columns includes a plurality of receiving surfaces for receiving a corresponding plurality of battery cells. Each of the plurality of cooling columns is further configured to deform when the second base in response to a force moves towards the first base.

Abstract: Provided are a computer program product for managing bus interface errors in a storage system coupled to a host and storage. A determination is made as to whether a first number of correctable errors on a first bus interface, connecting a first processing unit to the storage, exceeds a second number of correctable errors on a second bus interface, connecting a second processing unit to the storage, by a difference threshold. The correctable errors in the first and second bus interfaces are detected and corrected in the first and second bus interfaces by first hardware and second hardware, respectively. In response to determining that the first number of correctable errors exceeds the second number of correctable errors by the difference threshold, at least a portion of Input/Output (I/O) requests are redirected to a second processing unit using the second bus interface to connect to the storage.

Abstract: A method is disclosed to reduce lock contention in a data storage system. The method dispatches, on a first processor core, a task configured to acquire a lock on a data storage resource, such as memory. The method then determines whether the first processor core is associated with the data storage resource. If the first processor core is not associated with the data storage resource, the method re-dispatches the task on a second processor core that is associated with the data storage resource. In certain embodiments, the task is only re-dispatched on the second processor core if an amount of effort required to acquire the lock is above a selected threshold. If, on the other hand, the first processor core is associated with the data storage resource, the method executes the task on the first processor core. A corresponding system and computer program product are also disclosed.

Abstract: A first non-volatile dual in-line memory module (NVDIMM) of a first server and a second NVDIMM of a second server are armed during initial program load in a dual-server based storage system to configure the first NVDIMM and the second NVDIMM to retain data on power loss. Prior to initiating a safe data commit scan to destage modified data from the first server to a secondary storage, a determination is made as to whether the first NVDIMM is armed. In response to determining that the first NVDIMM is not armed, a failover is initiated to the second server.

Abstract: A method is disclosed to identify a port that is associated with a faulty cable. In one embodiment, such a method identifies a cable to replace. The cable provides a path between a first port, residing on a first component, and a second port, residing on a second component. The method further identifies whether an alternative path, bypassing the first cable, exists between the first component and the second component. In the event the alternative path exists, the method sends, over the alternative path, from the first component to the second component, a command to activate an indicator on the second port. This command is received and executed by the second component to activate the indicator. A corresponding apparatus and computer program product are also disclosed.

Abstract: In a computing storage environment having multiple processor devices, lists of Task Control Blocks (TCBs) are maintained in a processor-specific manner, such that each of the multiple processor devices is assigned a local TCB list. The local TCB list of each of the multiple processor devices is populated with a respective number of TCBs from a global TCB list. The local TCB list of each of the multiple processor devices exchanges TCBs with the global TCB list during processes to maintain the local TCB list of each of the multiple processor devices at the respective number.

Abstract: Provided are a computer program product, system, and method for managing processor threads of a plurality of processors. In one embodiment, a parameter of performance of the computing system is measured, and the configurations of one or more processor nodes are dynamically adjusted as a function of the measured parameter of performance. In this manner, the number of processor threads being concurrently executed by the plurality of processor nodes of the computing system may be dynamically adjusted in real time as the system operates to improve the performance of the system as it operates under various operating conditions. It is appreciated that systems employing processor thread management in accordance with the present description may provide other features in addition to or instead of those described herein, depending upon the particular application.

Abstract: Provided are a computer program product, system, and method for injecting trap code in an execution path of a process executing a program to generate a trap address range to detect potential malicious code. A specified type of command is processed in application code and, in response, trap code is executed to allocate a trap address range. The specified type of command is executed in the application code. A determination is made as to whether an accessing application accesses the trap address range. At least one of transmitting a notification that the accessing application comprises potentially malicious code, monitoring the execution of the accessing application, and restricting execution of the accessing application is performed in response to determining that the accessing application accessed the trap address range.

Abstract: An indication is made for each task category of a plurality of task categories, of a first attribute that indicates a data set to be collected, a second attribute that indicates a first predetermined amount of time within which a central processing unit (CPU) stops executing a task of the task category, and a third attribute that indicates a second predetermined amount of time within which the CPU that was executing the task of the task category collects the data set. In response to occurrence of an event, a plurality of CPUs are stopped to collect a plurality of data sets, based on first attributes, second attributes, and third attributes of task categories corresponding to tasks executing on the plurality of CPUs.

Abstract: A plurality of processing entities are maintained. An indication is made of a primary processing entities group for a task control block (TCB). An indication is made of a secondary processing entities group for the TCB. In response to determining that the secondary processing entities group has processing cycles available for processing additional TCBs, the TCB is moved from the primary processing entities group to the secondary processing entities group for processing.