Abstract: A determination is made as to whether a plurality of processing entities in a processor complex exceeds a predetermined threshold number. In response to determining that the plurality of processing entities exceeds the predetermined threshold number, a processing entity of the plurality of processing entities is reserved for exclusive execution of critical tasks. In response to determining that the plurality of processing entities does not exceed the predetermined threshold number, and in response to receiving a task that is a critical task for execution, a determination is made as to which processing entity of the plurality of processing entities has a least amount of processing remaining to be performed for currently scheduled tasks. In response to moving tasks queued on the determined processing entity to other processing entities, the critical task is scheduled for execution on the determined processing entity.

Abstract: A plurality of central processing units (CPUs) are allocated as a set of dedicated CPUs for processing tasks of an input/output (I/O) resource. In response to determining that a CPU utilization for the set of dedicated CPUs is less than a first predetermined threshold, at least one CPU of the set of dedicated CPUs is configured as a reserved CPU to execute tasks for one or more entities other than the I/O resource. In response to determining that a CPU utilization for the set of dedicated CPUs is greater than a second predetermined threshold, the reserved CPU is configured as a dedicated CPU to process tasks for the I/O resource.

Abstract: A plurality of dispatch queues corresponding to a plurality of processing entities are maintained, wherein each dispatch queue includes one or more task control blocks or is empty, and wherein an ordered list of dispatch queues is maintained for each processing entity of the plurality of processing entities. A state for each of the plurality of dispatch queues is determined and the determined state is compared to a desired state for the plurality of dispatch queues. A task control block is moved from one dispatch queue to another dispatch queue, in response to the comparing of the determined state to the desired state for the plurality of dispatch queues.

Abstract: Provided are a computer program product, system, and method for determining memory access categories to use to assign tasks to processor cores to execute. A computer system has a plurality of cores, each core is comprised of a plurality of processing units and at least one cache memory shared by the processing units on the core to cache data from a memory. At task is processed to determine one of the cores on which to dispatch the task. A memory access category of a plurality of memory access categories is determined to which the processed task is assigned. The processed task is dispatched to the core assigned the determined memory access category.

Abstract: A plurality of processing entities are maintained. An indication is made of a primary processing entities group for a task control block (TCB). An indication is made of a secondary processing entities group for the TCB. In response to determining that the secondary processing entities group has processing cycles available for processing additional TCBs, the TCB is moved from the primary processing entities group to the secondary processing entities group for processing.

Abstract: Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.

Abstract: Provided are a computer program product, system, and method to allocate a segment of a buffer to each of a plurality of threads to use for writing data. Each of a plurality of threads are assigned to one of a plurality of segments in a buffer, wherein the threads write to the segment to which they are assigned. A free segment list indicates segments which are not assigned to one of the threads. In response to one of the segments assigned to one of the threads becoming a full segment having less than a threshold amount of free space, indicating the full segment assigned to the thread in the free segment list and assigning one of the segments in the free segment list to the thread different from the full segment.

Abstract: Provided are a computer program product, system, and method for determining cores to assign to cache hostile tasks. A computer system has a plurality of cores. Each core is comprised of a plurality of processing units and at least one cache memory shared by the processing units on the core to cache data from a memory. A task is processed to determine one of the cores on which to dispatch the task. A determination is made as to whether the processed task is classified as cache hostile. A task is classified as cache hostile when the task accesses more than a threshold number of memory address ranges in the memory. The processed task is dispatched to at least one of the cores assigned to process cache hostile tasks.

Abstract: A set of like tasks to be performed is organized into a first group. A last used processing group assigned to the set of like tasks is stored. The set of like tasks is reassigned to an additional group having a minimal queue length upon a determination that the difference between the queue lengths of the additional processing group and the stored processing group is greater than a predetermined threshold.

Abstract: Provided are a computer program product, system, and method for monitoring correctable errors on a bus interface to determine whether to redirect traffic to another bus interface. A processing unit sends Input/Output (I/O) requests from a host to a storage over a first bus interface to a first device adaptor, wherein the first device adaptor provides a first connection to the storage. A determination is made as to whether a number of correctable errors on the first bus interface exceeds an error threshold. The correctable errors are detected and corrected in the first bus interface by hardware of the first bus interface. In response to determining that the number of correctable errors on the first bus interface exceeds the error threshold, at least a portion of I/O requests are redirected to use a second bus interface to connect to a second device adaptor providing a second connection to the storage.

Abstract: Mechanisms for improving computing system performance by a processor device. System resources are organized into a plurality of groups. Each of the plurality of groups is assigned one of a plurality of predetermined task pools. Each of the predetermined task pools has a plurality of tasks. Each of the plurality of groups corresponds to at least one physical boundary of the system resources such that a speed of an execution of those of the plurality of tasks for a particular one of the plurality of predetermined task pools is optimized by a placement of an association with the at least one physical boundary and the plurality of groups.

Abstract: Provided are a computer program product, system, and method for invoking Input/Output (I/O) threads on processors to demote tracks from a cache. An Input/Output (I/O) thread, executed by a processor, processes I/O requests directed to tracks in the storage by accessing the tracks in the cache. After processing at least one I/O request, the I/O thread determines whether a number of free cache segments in the cache is below a free cache segment threshold. The I/O thread processes a demote ready list, indicating tracks eligible to demote from the cache, to demote tracks from the cache in response to determining that the number of free cache segments is below the free cache segment threshold. The I/O thread continues to process I/O requests directed to tracks from the storage stored in the cache after processing the demote ready list to demote tracks in the cache.

Abstract: Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.

Abstract: Provided are a computer program product, system, and method for using send buffers and receive buffers for sending messages among nodes in a network. A send buffer is provided for each of at least one receiving node comprising one of the nodes to which messages are sent. Each of the receiving nodes includes at least one receive buffer to receive messages from the send buffer at the sending node. A determination is made of a buffer entry for a send buffer and receive buffer pair that is available for use. Indication is made of the message in the determined buffer entry of the send buffer. The message is sent from the send buffer to the receiving node indicating the determined buffer entry in which the message is indicated to cause the receiving node to include the message in the indicated buffer entry in the receive buffer.

Abstract: Provided are a computer program product, system, and method for determining cores to assign to cache hostile tasks. A computer system has a plurality of cores. Each core is comprised of a plurality of processing units and at least one cache memory shared by the processing units on the core to cache data from a memory. A task is processed to determine one of the cores on which to dispatch the task. A determination is made as to whether the processed task is classified as cache hostile. A task is classified as cache hostile when the task accesses more than a threshold number of memory address ranges in the memory. The processed task is dispatched to at least one of the cores assigned to process cache hostile tasks.

Abstract: Provided are a computer program product, system, and method for invoking Input/Output (I/O) threads on processors to demote tracks from a cache. An Input/Output (I/O) thread, executed by a processor, processes I/O requests directed to tracks in the storage by accessing the tracks in the cache. After processing at least one I/O request, the I/O thread determines whether a number of free cache segments in the cache is below a free cache segment threshold. The I/O thread processes a demote ready list, indicating tracks eligible to demote from the cache, to demote tracks from the cache in response to determining that the number of free cache segments is below the free cache segment threshold. The I/O thread continues to process I/O requests directed to tracks from the storage stored in the cache after processing the demote ready list to demote tracks in the cache.

Abstract: A battery packaging arrangement. The battery packaging arrangement includes a first base configured to be fixedly coupled to a frame of a vehicle, a second base moveable with respect to the first base, and a plurality of cooling columns inter-disposed between the first base and the second base. Each of the plurality of cooling columns includes a plurality of receiving surfaces for receiving a corresponding plurality of battery cells. Each of the plurality of cooling columns is further configured to deform when the second base in response to a force moves towards the first base.

Abstract: Provided are a computer program product, system, and method for invoking Input/Output (I/O) threads on processors to demote tracks from a cache. An Input/Output (I/O) thread, executed by a processor, processes I/O requests directed to tracks in the storage by accessing the tracks in the cache. After processing at least one I/O request, the I/O thread determines whether a number of free cache segments in the cache is below a free cache segment threshold. The I/O thread processes a demote ready list, indicating tracks eligible to demote from the cache, to demote tracks from the cache in response to determining that the number of free cache segments is below the free cache segment threshold. The I/O thread continues to process I/O requests directed to tracks from the storage stored in the cache after processing the demote ready list to demote tracks in the cache.

Abstract: Provided are a computer program product, system, and method for invoking demote threads on processors to demote tracks from a cache. A plurality of demote ready lists indicate tracks eligible to demote from the cache. In response to determining that a number of free cache segments in the cache is below a free cache segment threshold, a determination is made of a number of demote threads to invoke on processors based on the number of free cache segments and the free cache segment threshold. The determined number of demote threads are invoked to demote tracks in the cache indicated in the demote ready lists, wherein each invoked demote thread processes one of the demote ready lists to select tracks to demote from the cache to free cache segments in the cache.

Abstract: Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.