Patents by Inventor Trung N. NGUYEN

Trung N. NGUYEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9852075
    Abstract: Provided are a computer program product, system, and method to allocate a segment of a buffer to each of a plurality of threads to use for writing data. Each of a plurality of threads are assigned to one of a plurality of segments in a buffer, wherein the threads write to the segment to which they are assigned. A free segment list indicates segments which are not assigned to one of the threads. In response to one of the segments assigned to one of the threads becoming a full segment having less than a threshold amount of free space, indicating the full segment assigned to the thread in the free segment list and assigning one of the segments in the free segment list to the thread different from the full segment.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: December 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Herve G. P. Andre, Juan J. Ruiz, Trung N. Nguyen
  • Patent number: 9842016
    Abstract: In one aspect, multiple data path error collection is provided in a storage management system. In one embodiment, an error condition in a main data path between the storage controller and at least one of a host and a storage unit is detected, and in response, a sequence of error data collection operations to collect error data through a main path is initiated. In response to a failure to collect error data at a level of the sequential error data collection operations, error data is collected through an alternate data path as a function of the error data collection level at which the failure occurred. Other aspects are described.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: December 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gary W. Batchelor, Matthew D. Carson, Enrique Q. Garcia, Larry Juarez, Jay T. Kirch, Tony Leung, Trung N. Nguyen, Brian A. Rinaldi, Todd C. Sorenson
  • Patent number: 9842010
    Abstract: A computational device maintains a spinlock for exclusive access of a resource by a process of a plurality of processes. In response to determining by the process that a turn for securing the spinlock has not arrived for the process, a sleep duration is determined for the process, prior to making a next attempt to secure the spinlock.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: December 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Seamus J. Burke, Trung N. Nguyen, Louis A. Rasor
  • Publication number: 20170351545
    Abstract: A plurality of processing entities are maintained. An indication is made of a primary processing entities group for a task control block (TCB). An indication is made of a secondary processing entities group for the TCB. In response to determining that the secondary processing entities group has processing cycles available for processing additional TCBs, the TCB is moved from the primary processing entities group to the secondary processing entities group for processing.
    Type: Application
    Filed: June 3, 2016
    Publication date: December 7, 2017
    Inventors: Seamus J. Burke, Trung N. Nguyen, Louis A. Rasor
  • Publication number: 20170353396
    Abstract: A plurality of processing entities are maintained. A plurality of task control block (TCB) groups are generated, wherein each of the plurality of TCB groups are restricted to one or more different processing entities of the plurality of processing entities. A TCB is assigned to one of the plurality of TCB groups, at TCB creation time.
    Type: Application
    Filed: June 3, 2016
    Publication date: December 7, 2017
    Inventors: Seamus J. Burke, Trung N. Nguyen, Louis A. Rasor
  • Publication number: 20170351609
    Abstract: In one embodiment, storage drive dependent track removal processing logic performs destage tasks for tracks cached in a cache as a function of whether the storage drive is classified as a fast class or as slow class of storage drives, for example. In one embodiment, a destage task configured for a slow class storage drive, transfers an entry for a track selected for destaging from a main cache list to a wait cache list to await destaging to the slow class drive. A destage task configured for a fast class storage drive allows the cache list entry for the selected track to remain on the main cache list while the selected track is being destaged to the fast class storage drive, thereby bypassing the transfer of the entry to a wait cache list. Other features and aspects may be realized, depending upon the particular application.
    Type: Application
    Filed: June 2, 2016
    Publication date: December 7, 2017
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Publication number: 20170351432
    Abstract: Provided are a computer program product, system, and method for invoking Input/Output (I/O) threads on processors to demote tracks from a cache. An Input/Output (I/O) thread, executed by a processor, processes I/O requests directed to tracks in the storage by accessing the tracks in the cache. After processing at least one I/O request, the I/O thread determines whether a number of free cache segments in the cache is below a free cache segment threshold. The I/O thread processes a demote ready list, indicating tracks eligible to demote from the cache, to demote tracks from the cache in response to determining that the number of free cache segments is below the free cache segment threshold. The I/O thread continues to process I/O requests directed to tracks from the storage stored in the cache after processing the demote ready list to demote tracks in the cache.
    Type: Application
    Filed: June 6, 2016
    Publication date: December 7, 2017
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Publication number: 20170351618
    Abstract: Provided are a computer program product, system, and method for invoking demote threads on processors to demote tracks from a cache. A plurality of demote ready lists indicate tracks eligible to demote from the cache. In response to determining that a number of free cache segments in the cache is below a free cache segment threshold, a determination is made of a number of demote threads to invoke on processors based on the number of free cache segments and the free cache segment threshold. The determined number of demote threads are invoked to demote tracks in the cache indicated in the demote ready lists, wherein each invoked demote thread processes one of the demote ready lists to select tracks to demote from the cache to free cache segments in the cache.
    Type: Application
    Filed: June 6, 2016
    Publication date: December 7, 2017
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Publication number: 20170351549
    Abstract: A plurality of ordered lists of dispatch queues corresponding to a plurality of processing entities are maintained, wherein each dispatch queue includes one or more task control blocks or is empty. A determination is made as to whether a primary dispatch queue of a processing entity is empty in an ordered list of dispatch queues for the processing entity. In response to determining that the primary dispatch queue of the processing entity is empty, a task control block is selected for processing by the processing entity from another dispatch queue of the ordered list of dispatch queues for the processing entity, wherein the another dispatch queue from which the task control block is selected meets a threshold criteria for the processing entity.
    Type: Application
    Filed: June 3, 2016
    Publication date: December 7, 2017
    Inventors: Seamus J. Burke, Trung N. Nguyen, Louis A. Rasor
  • Publication number: 20170351611
    Abstract: Provided are a computer program product, system, and method for invoking Input/Output (I/O) threads and demote threads on processors to demote tracks from a cache. An Input/Output (I/O) thread, executed by a processor, processes I/O requests directed to tracks from the storage stored in the cache. A demote thread, executed by the processor, processes a demote ready list, indicating tracks eligible to demote from cache, to select tracks to demote from the cache to free cache segments in the cache. After processing a number of I/O requests, the I/O thread processes the demote ready list to demote tracks from the cache in response to determining that a number of free cache segments in the cache is below a free cache segment threshold.
    Type: Application
    Filed: June 6, 2016
    Publication date: December 7, 2017
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Publication number: 20170344265
    Abstract: Provided are a computer program product, system, and method for selecting resources to make available in local queues for processors to use. Each processor of a plurality of processors maintains a queue of resources for the processor to use when needed for processor operations. One of processors is selected. The selected processor accesses at least one available resource and includes the accessed at least one resource in the queue of the selected processor.
    Type: Application
    Filed: May 26, 2016
    Publication date: November 30, 2017
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Patent number: 9798466
    Abstract: Provided are a computer program product, system, and method for using a plurality of sub-buffers and a free segment list to allocate segments to a plurality of threads to use for writing data. Groups of threads are assigned to sub-buffers. At least one segment of data is indicated in each of the sub-buffers. The threads assigned to one of the sub-buffers write to the at least one segment indicated in the sub-buffer to which the threads are assigned. A free segment list indicates segments which are not indicated in one of the sub-buffers. In response to one of the segments in a containing sub-buffer comprising one of the sub-buffers becoming a full segment having less than a threshold amount of free space, the indication of the full segment in the containing sub-buffer is replaced with one of the segments indicated in the free segment list.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: October 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Herve G. P. Andre, Juan J. Ruiz, Trung N. Nguyen
  • Patent number: 9772785
    Abstract: A rack-power control module (RPC) module is used for allowing a local storage partition, located on a local server, for controlling a destination storage partition, located on a destination server, by piggybacking commands on power alerts issued by the RPC module in a clustered storage system. The commands are sent from the local storage partition to the RPC module, where the commands are RPC commands and include a destination server identification (ID) and payload data that includes a hypervisor command containing a command type, a subtype, and a destination ID. The RPC module then parses the commands received from the local storage partition.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: September 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yolanda Colpo, Larry Juarez, Trung N. Nguyen, Sean P. Riley
  • Patent number: 9766982
    Abstract: A determination is made of a plurality of components whose states are to be determined to generate a statesave. At least one central processing unit that determines a state of a first component of the plurality of components faster than other central processing units is assigned to determine the state of the first component to include in the statesave, where more processing operations have to be performed to determine the state of the first component in comparison to any other component of the plurality of component. One or more of the other central processing units are assigned to other components of the plurality of components to determine states of the other components to include in the statesave.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: September 19, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Trung N. Nguyen, Maoyun Tang
  • Patent number: 9753773
    Abstract: In one embodiment of multi-mode task dispatching for extreme temperature avoidance, a performance-based dispatching mode includes a heating sub-mode in which heat generating non-system workload tasks are dispatched to idle processor cores of a set of available processor cores to raise the temperature of processing cores receiving a heat generating task. The heating sub-mode is entered if a multi-processor core temperature such as the ambient temperature of a CPU complex, for example, is below a sub-mode temperature threshold value. In this manner, the ambient temperature of the CPU complex may be prevented from reaching or maintaining a level which causes the CPU complex to fully or partially shut down due to low temperatures. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: September 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Patent number: 9747139
    Abstract: In one embodiment, performance-based multi-mode task dispatching for high temperature avoidance in accordance with the present description, includes selecting processor cores as available to receive a dispatched task. Tasks are dispatched to a set of available processor cores for processing in a performance-based dispatching mode. If monitored temperature rises above a threshold temperature value, task dispatching logic switches to a thermal-based dispatching mode. If a monitored temperature falls below another threshold temperature value, dispatching logic switches back to the performance-based dispatching mode. If a monitored temperature of an individual processor core rises above a threshold temperature value, the processor core is redesignated as unavailable to receive a dispatched task. If the temperature of an individual processor core falls below another threshold temperature value, the processor core is redesignated as available to receive a dispatched task.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: August 29, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Patent number: 9747210
    Abstract: Provided are a computer program product, system, and method for managing a lock to a resource shared among a plurality of processors. Slots in a memory implement the lock on the shared resource. The slots correspond to counter values that are consecutively numbered and indicate one of busy and free. A requesting processor fetches a counter value comprising a fetched counter value. A determination is made as to whether the slot corresponding to the fetched counter value indicates free. A processor identifier of the requesting processor is inserted into the slot corresponding to the fetched counter value in response to determining that the slot corresponding to the fetched counter value indicates not free. The requesting processor accesses the shared resource in response to determining that the slot corresponding to the fetched counter value indicates free.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: August 29, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Trung N. Nguyen
  • Publication number: 20170147494
    Abstract: Provided are a computer program product, system, and method to allocate a segment of a buffer to each of a plurality of threads to use for writing data. Each of a plurality of threads are assigned to one of a plurality of segments in a buffer, wherein the threads write to the segment to which they are assigned. A free segment list indicates segments which are not assigned to one of the threads. In response to one of the segments assigned to one of the threads becoming a full segment having less than a threshold amount of free space, indicating the full segment assigned to the thread in the free segment list and assigning one of the segments in the free segment list to the thread different from the full segment.
    Type: Application
    Filed: November 20, 2015
    Publication date: May 25, 2017
    Inventors: Herve G.P. Andre, Juan J. Ruiz, Trung N. Nguyen
  • Publication number: 20170147049
    Abstract: A storage controller determines a presence of an indication from an Input/Output (I/O) enclosure that the I/O enclosure will be powered off after a predetermined amount of time. The storage controller quiesces all I/O adapters of the I/O enclosure, in response to receiving the indication. The storage controller quiesces the I/O enclosure, in response to completion of quiescing of all of the I/O adapters of the I/O enclosure.
    Type: Application
    Filed: November 20, 2015
    Publication date: May 25, 2017
    Inventors: Herve G. P. Andre, Gary W. Batchelor, Scott A. Brewer, Veronica S. Davila, Enrique Q. Garcia, Daniel I. Ibanez, Trung N. Nguyen, Louis A. Rasor, Brian A. Rinaldi, Micah Robison, Todd C. Sorenson
  • Publication number: 20170147223
    Abstract: Provided are a computer program product, system, and method for using a plurality of sub-buffers and a free segment list to allocate segments to a plurality of threads to use for writing data. Groups of threads are assigned to sub-buffers. At least one segment of data is indicated in each of the sub-buffers. The threads assigned to one of the sub-buffers write to the at least one segment indicated in the sub-buffer to which the threads are assigned. A free segment list indicates segments which are not indicated in one of the sub-buffers. In response to one of the segments in a containing sub-buffer comprising one of the sub-buffers becoming a full segment having less than a threshold amount of free space, the indication of the full segment in the containing sub-buffer is replaced with one of the segments indicated in the free segment list.
    Type: Application
    Filed: August 18, 2016
    Publication date: May 25, 2017
    Inventors: Herve G.P. Andre, Juan J. Ruiz, Trung N. Nguyen