Abstract: Provided are techniques for detecting a type of storage adapter connected to an Input/Output (I/O) bay and miscabling of a microbay housing the storage adapter. Under control of an Input/Ouput (I/O) bay, cable sidebands are driven high for a predetermined period of time. It is determined whether a cable sidebands response has been detected that indicates that the cable sidebands have been driven low. In response to determining that the cable sidebands response has been detected, it is determined that the I/O bay is connected to a first storage adapter supporting a first protocol for the cable sidebands. In response to determining that the cable sidebands response has not been detected, it is determined that the I/O bay is connected to a second storage adapter supporting a second protocol for the cable sidebands. Moreover, I/O bay and port numbers stored by the microbay are used to determine miscabling.

Abstract: A background process is configured to periodically scrub a boot storage of a storage controller to ensure operational correctness of the boot storage. One or more foreground processes store a system configuration data of the storage controller in the boot storage of the storage controller. The background process and the one or more foreground processes are executed to meet predetermined performance requirements for the background process and the one or more foreground processes.

Abstract: Provided are techniques for lock profiling tool to identify code bottlenecks. A lock spin duration for a lock is determined. It is determined that the lock spin duration is greater than a lock trace threshold. The lock spin duration is classified into a time duration bucket. It is determining whether the lock is found in a list of locks for the time duration bucket. In response to determining that the lock is found in the list of locks, a lock count for the lock is incremented by one. In response to determining that the lock is not found in the list of locks, an entry for the lock is added in the list of locks for the time duration bucket and the lock count for the lock is initialized to one. A total spin duration time for the lock is updated by the lock spin duration.

Abstract: Provided are a computer program product, system, and method for invoking Input/Output (I/O) threads on processors to demote tracks from a cache. An Input/Output (I/O) thread, executed by a processor, processes I/O requests directed to tracks in the storage by accessing the tracks in the cache. After processing at least one I/O request, the I/O thread determines whether a number of free cache segments in the cache is below a free cache segment threshold. The I/O thread processes a demote ready list, indicating tracks eligible to demote from the cache, to demote tracks from the cache in response to determining that the number of free cache segments is below the free cache segment threshold. The I/O thread continues to process I/O requests directed to tracks from the storage stored in the cache after processing the demote ready list to demote tracks in the cache.

Abstract: Provided are a computer program product, system, and method for invoking Input/Output (I/O) threads and demote threads on processors to demote tracks from a cache. An Input/Output (I/O) thread, executed by a processor, processes I/O requests directed to tracks from the storage stored in the cache. A demote thread, executed by the processor, processes a demote ready list, indicating tracks eligible to demote from cache, to select tracks to demote from the cache to free cache segments in the cache. After processing a number of I/O requests, the I/O thread processes the demote ready list to demote tracks from the cache in response to determining that a number of free cache segments in the cache is below a free cache segment threshold.

Abstract: A computational device maintains a spinlock for exclusive access of a resource by a process of a plurality of processes. In response to determining by the process that a turn for securing the spinlock has not arrived for the process, a sleep duration is determined for the process, prior to making a next attempt to secure the spinlock.

Abstract: A determination is made as to whether a plurality of processing entities in a processor complex exceeds a predetermined threshold number. In response to determining that the plurality of processing entities exceeds the predetermined threshold number, a processing entity of the plurality of processing entities is reserved for exclusive execution of critical tasks. In response to determining that the plurality of processing entities does not exceed the predetermined threshold number, and in response to receiving a task that is a critical task for execution, a determination is made as to which processing entity of the plurality of processing entities has a least amount of processing remaining to be performed for currently scheduled tasks. In response to moving tasks queued on the determined processing entity to other processing entities, the critical task is scheduled for execution on the determined processing entity.

Abstract: A plurality of processing entities of a processor complex is maintained, wherein each processing entity has a local cache and the processor complex has a shared cache and a shared memory. One of the plurality of processing entities is allocated for execution of a critical task. In response to the allocating of one of the plurality of processing entities for the execution of the critical task, other processing entities of the plurality of processing entities are folded. The critical task utilizes the local cache of the other processing entities that are folded, the shared memory, and the shared cache, in addition to the local cache of the processing entity allocated for the execution of the critical task.

Abstract: Provided are a computer program product, system, and method for invoking demote threads on processors to demote tracks from a cache. A plurality of demote ready lists indicate tracks eligible to demote from the cache. In response to determining that a number of free cache segments in the cache is below a free cache segment threshold, a determination is made of a number of demote threads to invoke on processors based on the number of free cache segments and the free cache segment threshold. The determined number of demote threads are invoked to demote tracks in the cache indicated in the demote ready lists, wherein each invoked demote thread processes one of the demote ready lists to select tracks to demote from the cache to free cache segments in the cache.

Abstract: In one embodiment, performance-based multi-mode task dispatching for high temperature avoidance in accordance with the present description, includes selecting processor cores as available to receive a dispatched task. Tasks are dispatched to a set of available processor cores for processing in a performance-based dispatching mode. If monitored temperature rises above a threshold temperature value, task dispatching logic switches to a thermal-based dispatching mode. If a monitored temperature falls below another threshold temperature value, dispatching logic switches back to the performance-based dispatching mode. If a monitored temperature of an individual processor core rises above a threshold temperature value, the processor core is redesignated as unavailable to receive a dispatched task. If the temperature of an individual processor core falls below another threshold temperature value, the processor core is redesignated as available to receive a dispatched task.

Abstract: Provided are a computer program product, system, and method for managing processor threads of a plurality of processors. In one embodiment, a parameter of performance of the computing system is measured, and the configurations of one or more processor nodes are dynamically adjusted as a function of the measured parameter of performance. In this manner, the number of processor threads being concurrently executed by the plurality of processor nodes of the computing system may be dynamically adjusted in real time as the system operates to improve the performance of the system as it operates under various operating conditions. It is appreciated that systems employing processor thread management in accordance with the present description may provide other features in addition to or instead of those described herein, depending upon the particular application.

Abstract: A plurality of processing entities in which a plurality of tasks are executed are maintained. Memory access patterns are determined for each of the plurality of tasks by dividing a memory associated with the plurality of processing entities into a plurality of memory regions, and for each of the plurality of tasks, determining how many memory accesses take place in each of the memory regions, by incrementing a counter associated with each memory region in response to a memory access. Each of the plurality of tasks are allocated among the plurality of processing entities, based on the determined memory access patterns for each of the plurality of tasks.

Abstract: Provided are a computer program product, system, and method for determining memory access categories to use to assign tasks to processor cores to execute. A computer system has a plurality of cores, each core is comprised of a plurality of processing units and at least one cache memory shared by the processing units on the core to cache data from a memory. At task is processed to determine one of the cores on which to dispatch the task. A memory access category of a plurality of memory access categories is determined to which the processed task is assigned. The processed task is dispatched to the core assigned the determined memory access category.

Abstract: Provided are a computer program product, system, and method for determining cores to assign to cache hostile tasks. A computer system has a plurality of cores. Each core is comprised of a plurality of processing units and at least one cache memory shared by the processing units on the core to cache data from a memory. A task is processed to determine one of the cores on which to dispatch the task. A determination is made as to whether the processed task is classified as cache hostile. A task is classified as cache hostile when the task accesses more than a threshold number of memory address ranges in the memory. The processed task is dispatched to at least one of the cores assigned to process cache hostile tasks.

Abstract: Provided are a computer program product, system, and method to allocate a segment of a buffer to each of a plurality of threads to use for writing data. Each of a plurality of threads are assigned to one of a plurality of segments in a buffer, wherein the threads write to the segment to which they are assigned. A free segment list indicates segments which are not assigned to one of the threads. In response to one of the segments assigned to one of the threads becoming a full segment having less than a threshold amount of free space, indicating the full segment assigned to the thread in the free segment list and assigning one of the segments in the free segment list to the thread different from the full segment.

Abstract: In one aspect, multiple data path error collection is provided in a storage management system. In one embodiment, an error condition in a main data path between the storage controller and at least one of a host and a storage unit is detected, and in response, a sequence of error data collection operations to collect error data through a main path is initiated. In response to a failure to collect error data at a level of the sequential error data collection operations, error data is collected through an alternate data path as a function of the error data collection level at which the failure occurred. Other aspects are described.

Abstract: A plurality of cores are maintained in a processor complex. A core of the plurality of cores is reserved for execution of critical tasks, wherein it is preferable to prioritize execution of critical tasks over non-critical tasks. A scheduler receives a task for scheduling in the plurality of cores. In response to determining that the task is a critical task, the task is scheduled for execution in the reserved core.

Abstract: A plurality of processing entities are maintained in a processor complex. In response to determining that a task is a critical task, the critical task is dispatched to a scheduler, wherein it is preferable to prioritize execution of critical tasks over non-critical tasks. In response to dispatching the critical task to the scheduler, the scheduler determines which processing entity of the plurality of processing entities has a least amount of processing remaining to be performed for currently scheduled tasks. Tasks queued on the determined processing entity are moved to other processing entities, and the currently scheduled tasks on the determined processing entity are completed. In response to moving tasks queued on the determined processing entity to other processing entities and completing the currently scheduled tasks on the determined processing entity, the critical task is dispatched on the determined processing entity.

Abstract: A storage controller determines a presence of an indication from an Input/Output (I/O) enclosure that the I/O enclosure will be powered off after a predetermined amount of time. The storage controller quiesces all I/O adapters of the I/O enclosure, in response to receiving the indication. The storage controller quiesces the I/O enclosure, in response to completion of quiescing of all of the I/O adapters of the I/O enclosure.

Abstract: Provided are a computer program product, system, and method for managing processor threads of a plurality of processors. In one embodiment, a parameter of performance of the computing system is measured, and the configurations of one or more processor nodes are dynamically adjusted as a function of the measured parameter of performance. In this manner, the number of processor threads being concurrently executed by the plurality of processor nodes of the computing system may be dynamically adjusted in real time as the system operates to improve the performance of the system as it operates under various operating conditions. It is appreciated that systems employing processor thread management in accordance with the present description may provide other features in addition to or instead of those described herein, depending upon the particular application.