Abstract: A plurality of central processing units (CPUs) are allocated as a set of dedicated CPUs for processing tasks of an input/output (I/O) resource. In response to determining that a CPU utilization for the set of dedicated CPUs is less than a first predetermined threshold, at least one CPU of the set of dedicated CPUs is configured as a reserved CPU to execute tasks for one or more entities other than the I/O resource. In response to determining that a CPU utilization for the set of dedicated CPUs is greater than a second predetermined threshold, the reserved CPU is configured as a dedicated CPU to process tasks for the I/O resource.

Abstract: Different example implementations of the present disclosure relates to methods and computer readable mediums for automatically generating physically aware NoC design and physically aware NoC Specification based on one or more of given SoC architectural details, physical information of SoC, traffic specification, power profile and one or more constraints. The method includes steps of receiving input information, determining the location/position of different NoC agents, interconnecting channels, pins, I/O interfaces, physical/virtual boundaries, number of layers, size/depth/width of different channels at different time, and locating/configuring the different NoC agents, interconnecting channels, pins, I/O interfaces, and physical/virtual boundaries.

Abstract: A cloud-based migration system exposes a source-independent application programming interface for receiving data to be migrated. The data is uploaded and stored as a single entity in a cloud-based storage system. A migration system then accesses the migration package and begins migrating the data to its destination, from the cloud-based storage system.

Abstract: A plurality of dispatch queues corresponding to a plurality of processing entities are maintained, wherein each dispatch queue includes one or more task control blocks or is empty, and wherein an ordered list of dispatch queues is maintained for each processing entity of the plurality of processing entities. A state for each of the plurality of dispatch queues is determined and the determined state is compared to a desired state for the plurality of dispatch queues. A task control block is moved from one dispatch queue to another dispatch queue, in response to the comparing of the determined state to the desired state for the plurality of dispatch queues.

Abstract: A motor drive system for operating a mechanism for raising and lowering window coverings includes a motor operating under electrical power and an electrically powered drive system. The motor drive system advances a continuous cord loop in response to positional commands from a controller. An input-output device includes a capacitive touch strip that receives user inputs along an input axis, and an LEDs strip aligned with the input axis. A group mode module communicates the positional commands to other motor drive systems within an identified group to operate respective other mechanisms of the other motor drive systems. A set control module enables user calibration of a top position and a bottom position of travel of the window covering. The input-output device extends vertically on the exterior of a housing for the motor drive system, and the housing supports input buttons of the group mode module and the set control module.

Abstract: Provided are a computer program product, system, and method for determining memory access categories to use to assign tasks to processor cores to execute. A computer system has a plurality of cores, each core is comprised of a plurality of processing units and at least one cache memory shared by the processing units on the core to cache data from a memory. At task is processed to determine one of the cores on which to dispatch the task. A memory access category of a plurality of memory access categories is determined to which the processed task is assigned. The processed task is dispatched to the core assigned the determined memory access category.

Abstract: In embodiments, a method of forming a membrane electrode assembly comprises pressing a stack comprising a cathode, an anode, a proton exchange membrane between the cathode and the anode, and a porous catalyst layer in contact with the proton exchange membrane, the porous catalyst layer comprising an ionomer, the ionomer coating internal surfaces of pores of the porous catalyst layer, thereby providing internal ionomer-gas interfaces within the porous catalyst layer; for a time, a pressure, and a temperature to bind the ionomer to the proton exchange membrane, whereby steam is generated within the porous catalyst layer. The steam is removed via pores of the porous catalyst layer to increase the hydrophobicity of the internal ionomer-gas interfaces within the porous catalyst layer.

Abstract: The present invention relates to a rotor for a pyrolysis centrifuge reactor, said rotor comprising a rotor body having a longitudinal center axis, and at least one pivotally mounted blade being adapted to pivot around a pivot axis under rotation of the rotor body around the longitudinal center axis. Moreover, the present invention relates to a pyrolysis centrifuge reactor applying such a rotor.

Abstract: Embodiments are directed to techniques for providing a user-selected target resistance across a set of output terminals of a resistance-generating apparatus.

Abstract: A plurality of processing entities are maintained. An indication is made of a primary processing entities group for a task control block (TCB). An indication is made of a secondary processing entities group for the TCB. In response to determining that the secondary processing entities group has processing cycles available for processing additional TCBs, the TCB is moved from the primary processing entities group to the secondary processing entities group for processing.

Abstract: Provided are techniques for concurrent Input/Output (I/O) enclosure firmware/Field-Programmable Gate Array (FPGA) update in a multi-node environment. First notifications are sent to each I/O enclosure management engine on each of a plurality of server nodes that code activation for a first set of I/O enclosures is starting. An update image is distributed to the first set of I/O enclosures. The update image on the first set of I/O enclosures is activated by sending an activate reset command to each of the first set of I/O enclosures, wherein a reset is not propagated to other devices within each I/O enclosure in the first set of I/O enclosures in response to determining that the reset is an activate reset. In response to the activate reset command completing, second notifications are sent to each I/O enclosure management engine that code activation for the first set of I/O enclosures has completed.

Abstract: Provided are a computer program product, system, and method to allocate a segment of a buffer to each of a plurality of threads to use for writing data. Each of a plurality of threads are assigned to one of a plurality of segments in a buffer, wherein the threads write to the segment to which they are assigned. A free segment list indicates segments which are not assigned to one of the threads. In response to one of the segments assigned to one of the threads becoming a full segment having less than a threshold amount of free space, indicating the full segment assigned to the thread in the free segment list and assigning one of the segments in the free segment list to the thread different from the full segment.

Abstract: Provided are a computer program product, system, and method for determining cores to assign to cache hostile tasks. A computer system has a plurality of cores. Each core is comprised of a plurality of processing units and at least one cache memory shared by the processing units on the core to cache data from a memory. A task is processed to determine one of the cores on which to dispatch the task. A determination is made as to whether the processed task is classified as cache hostile. A task is classified as cache hostile when the task accesses more than a threshold number of memory address ranges in the memory. The processed task is dispatched to at least one of the cores assigned to process cache hostile tasks.

Abstract: An electronic system provides various features and functionality for managing resources. An alert may be sent when a mobile device crosses a geo-fence. The alert may describe how much of the resource is available for the types of transaction that are likely to occur within the geo-fence. The alert may request or confirm the allocation of the transaction to a resource pool or suggest alternative transactions.

Abstract: The present invention is directed towards providing automated workflows for the identification of a reading order from text segments extracted from a document. Ordering the text segments is based on trained natural language models. In some embodiments, the workflows are enabled to perform a method for identifying a sequence associated with a portable document. The methods includes iteratively generating a probabilistic language model, receiving the portable document, and selectively extracting features (such as but not limited to text segments) from the document. The method may generate pairs of features (or feature pair from the extracted features). The method may further generate a score for each of the pairs based on the probabilistic language model and determine an order to features based on the scores. The method may provide the extracted features in the determined order.

Abstract: Automatically transferring transmissions of a data network in which one or more processors receive metrics of active concurrent transmission sessions on a LAN that includes a data network, connected to a WAN, and a threshold level of concurrent transmission sessions of the data network of the LAN. Receiving a request for an additional transmission session, and responsive to determining that the threshold level of concurrent transmission sessions is exceeded, accessing data that maps a communication connection of the data network for a targeted recipient, to a communication connection of an alternate network corresponding to the targeted recipient, and performing a transfer of the additional transmission session from the communication connection of the data network for the targeted recipient, to the alternate network corresponding to the targeted recipient.

Abstract: A component is a building block having a pair of parallel load-bearing concrete side walls separated by a gap and joined by crossed metal ties which bridge the gap. The outer faces of the side walls can be covered with a decorative finish such as stone. The blocks have an added end wall which enables pillars to be built. The method of casting the blocks utilizes a collapsible metal mold which permits the side walls to be stepped.

Abstract: A set of like tasks to be performed is organized into a first group. A last used processing group assigned to the set of like tasks is stored. The set of like tasks is reassigned to an additional group having a minimal queue length upon a determination that the difference between the queue lengths of the additional processing group and the stored processing group is greater than a predetermined threshold.

Abstract: Provided are a computer program product, system, and method for monitoring correctable errors on a bus interface to determine whether to redirect traffic to another bus interface. A processing unit sends Input/Output (I/O) requests from a host to a storage over a first bus interface to a first device adaptor, wherein the first device adaptor provides a first connection to the storage. A determination is made as to whether a number of correctable errors on the first bus interface exceeds an error threshold. The correctable errors are detected and corrected in the first bus interface by hardware of the first bus interface. In response to determining that the number of correctable errors on the first bus interface exceeds the error threshold, at least a portion of I/O requests are redirected to use a second bus interface to connect to a second device adaptor providing a second connection to the storage.

Abstract: Provided are a computer program product for managing bus interface errors in a storage system coupled to a host and storage. A determination is made as to whether a first number of correctable errors on a first bus interface, connecting a first processing unit to the storage, exceeds a second number of correctable errors on a second bus interface, connecting a second processing unit to the storage, by a difference threshold. The correctable errors in the first and second bus interfaces are detected and corrected in the first and second bus interfaces by first hardware and second hardware, respectively. In response to determining that the first number of correctable errors exceeds the second number of correctable errors by the difference threshold, at least a portion of Input/Output (I/O) requests are redirected to a second processing unit using the second bus interface to connect to the storage.