Patents by Inventor Tsiao-Chen Wu

Tsiao-Chen Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8124323
    Abstract: The method of patterning a photosensitive layer includes providing a substrate including a first layer formed thereon, treating the substrate including the first layer with cations, forming a first photosensitive layer over the first layer, patterning the first photosensitive layer to form a first pattern, treating the first pattern with cations, forming a second photosensitive layer over the treated first pattern, patterning the second photosensitive layer to form a second pattern, and processing the first layer using the first and second patterns as a mask.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: February 28, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tzu Lu, Keui Shun Chen, Tsiao-Chen Wu, Vencent Chang, George Liu
  • Patent number: 7838173
    Abstract: The present disclosure provides a mask. The mask includes a substrate; a first attenuating layer disposed on the substrate, having a first material and a first thickness corresponding to a phase shift; and a second attenuating layer having a second material and disposed on the first attenuating layer. The first and second attenuating layers define a first feature having a first opening extending through the first and second attenuating layers; and a second feature having a second opening extending through the second attenuating layer and exposing the first attenuating layer. One of the first and second features is a main feature and the other one is an assistant feature proximate to the main feature.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: November 23, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya Hui Chang, Tsiao Chen Wu, Shih-Che Wang
  • Publication number: 20100053575
    Abstract: A method of patterning an integrated circuit including generating a thermal profile of a reticle is provided. The thermal profile of the reticle may illustrate heat accumulation (e.g., a temperature) in a EUV reticle due an incident EUV radiation beam. The thermal profile may be determined using the pattern density of the reticle. The reticle is irradiated with a radiation beam having an extreme ultraviolet (EUV) wavelength. A thermal control profile may be generated using the thermal profile, which may define a parameter of the lithography process such as, a temperature gradient of a thermal control chuck. The thermal control profile may be downloaded to the EUV lithography tool (e.g., scanner or stepper) for use in a process. A separate thermal control profile may be provided for different reticles.
    Type: Application
    Filed: September 4, 2008
    Publication date: March 4, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: I-Hsiung Huang, Tsiao-Chen Wu, Hsin-Chang Lee, Anthony Yen
  • Publication number: 20090081591
    Abstract: The method of patterning a photosensitive layer includes providing a substrate including a first layer formed thereon, treating the substrate including the first layer with cations, forming a first photosensitive layer over the first layer, patterning the first photosensitive layer to form a first pattern, treating the first pattern with cations, forming a second photosensitive layer over the treated first pattern, patterning the second photosensitive layer to form a second pattern, and processing the first layer using the first and second patterns as a mask.
    Type: Application
    Filed: September 25, 2007
    Publication date: March 26, 2009
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Tzu Lu, Keui Shun Chen, Tsiao-Chen Wu, Vencent Chang, George Liu
  • Publication number: 20080156346
    Abstract: A method for photolithography processing includes forming a photoresist layer on a surface of a substrate, baking the substrate to remove solvents from the photoresist layer, cleaning an edge of the substrate with a tape, and exposing the photoresist layer with radiation energy. The tape includes a cleaning material. The tape is positioned proximate to or in contact with the edge of the substrate while the substrate is rotating.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Cheng Wang, Hung Chang Hsieh, Tsiao-Chen Wu, Jian-Hong Chen
  • Publication number: 20080131790
    Abstract: The present disclosure provides a mask. The mask includes a substrate; a first attenuating layer disposed on the substrate, having a first material and a first thickness corresponding to a phase shift; and a second attenuating layer having a second material and disposed on the first attenuating layer. The first and second attenuating layers define a first feature having a first opening extending through the first and second attenuating layers; and a second feature having a second opening extending through the second attenuating layer and exposing the first attenuating layer. One of the first and second features is a main feature and the other one is an assistant feature proximate to the main feature.
    Type: Application
    Filed: December 1, 2006
    Publication date: June 5, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya Hui Chang, Tsiao Chen Wu, Shih-Che Wang
  • Patent number: 7169701
    Abstract: A method for forming a dual damascene including providing a first dielectric insulating layer including a via opening; forming an organic dielectric layer over the first IMD layer to include filling the via opening; forming a hardmask layer over the organic dielectric layer; photolithographically patterning and dry etching the hardmask layer and organic dielectric layer to leave a dummy portion overlying the via opening; forming an oxide liner over the dummy portion; forming a second dielectric insulating layer over the oxide liner to surround the dummy portion; planarizing the second dielectric insulating layer to expose the upper portion of the dummy portion; and, removing the organic dielectric layer to form a dual damascene opening including the oxide liner lining trench line portion sidewalls.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: January 30, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Nan Yeh, Tsiao-Chen Wu, Chao-Cheng Chen
  • Publication number: 20060003576
    Abstract: A method for forming a dual damascene including providing a first dielectric insulating layer including a via opening; forming an organic dielectric layer over the first IMD layer to include filling the via opening; forming a hardmask layer over the organic dielectric layer; photolithographically patterning and dry etching the hardmask layer and organic dielectric layer to leave a dummy portion overlying the via opening; forming an oxide liner over the dummy portion; forming a second dielectric insulating layer over the oxide liner to surround the dummy portion; planarizing the second dielectric insulating layer to expose the upper portion of the dummy portion; and, removing the organic dielectric layer to form a dual damascene opening including the oxide liner lining trench line portion sidewalls.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventors: Chen-Nan Yeh, Tsiao-Chen Wu, Chao-Cheng Chen
  • Patent number: 6383693
    Abstract: A method for forming a patterned target layer from a blanket target layer while employing a blanket photoresist layer in conjunction with an exposure method which is susceptible to a proximity effect employs when exposing the blanket photoresist layer to form an exposed blanket photoresist layer a main latent pattern and a second latent pattern adjacent the main latent pattern. Each patterned photoresist layer formed upon developing the main latent pattern is formed of a first linewidth such that not all of a first portion of the blanket target layer formed therebeneath is etched within an isotropic etchant which is employed for etching the blanket target layer to form the patterned target layer.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: May 7, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsiao-Chen Wu, Fei-Gwo Tsai