Patents by Inventor Tsiu C. Chan
Tsiu C. Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 5955770Abstract: A method is provided for forming a planar transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A plurality of field oxide regions are formed overlying a substrate electrically isolating a plurality of transistors encapsulated in a dielectric. LDD regions are formed in the substrate adjacent the transistors and the field oxide regions. Doped polysilicon raised source and drain regions are formed overlying the LDD regions and a tapered portion of the field oxide region and adjacent the transistor. These polysilicon raised source and drain regions will help to prevent any undesired amount of the substrate silicon from being consumed, reducing the possibility of junction leakage and punchthrough as well as providing a more planar surface for subsequent processing steps.Type: GrantFiled: June 18, 1997Date of Patent: September 21, 1999Assignee: STMicroelectronics, Inc.Inventors: Tsiu C. Chan, Gregory C. Smith
-
Patent number: 5894160Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.Type: GrantFiled: October 3, 1996Date of Patent: April 13, 1999Assignee: STMicroelectronics, Inc.Inventors: Tsiu C. Chan, Frank R. Bryant, Loi N. Nguyen
-
Patent number: 5770892Abstract: A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active region in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SRAM cells.Type: GrantFiled: June 2, 1995Date of Patent: June 23, 1998Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Tsiu C. Chan, Yu-Pin Han, Elmer H. Guritz
-
Patent number: 5705427Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.Type: GrantFiled: April 11, 1995Date of Patent: January 6, 1998Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Tsiu C. Chan, Frank R. Bryant, Loi N. Nguyen, Artur P. Balasinski
-
Patent number: 5702979Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.Type: GrantFiled: December 22, 1994Date of Patent: December 30, 1997Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Tsiu C. Chan, Frank R. Bryant, Loi N. Nguyen
-
Patent number: 5683924Abstract: A method is provided for forming a planar transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A plurality of field oxide regions are formed overlying a substrate electrically isolating a plurality of transistors encapsulated in a dielectric. LDD regions are formed in the substrate adjacent the transistors and the field oxide regions. Doped polysilicon raised source and drain regions are formed overlying the LDD regions and a tapered portion of the field oxide region and adjacent the transistor. These polysilicon raised source and drain regions will help to prevent any undesired amount of the substrate silicon from being consumed, reducing the possibility of junction leakage and punchthrough as well as providing a more planar surface for subsequent processing steps.Type: GrantFiled: June 7, 1995Date of Patent: November 4, 1997Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Tsiu C. Chan, Gregory C. Smith
-
Patent number: 5682055Abstract: A method is provided for forming an improved planar structure of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A field oxide is grown across the integrated circuit patterned and etched to form an opening with substantially vertical sidewalls exposing a portion of an upper surface of a substrate underlying the field oxide where an active area will be formed. A gate electrode comprising a polysilicon gate electrode and a gate oxide are formed over the exposed portion of the substrate. The polysilicon gate has a height at its upper surface above the substrate at or above the height of the upper surface of the field oxide. The gate electrode preferably also comprises a silicide above the polysilicon and an oxide capping layer above the silicide. LDD regions are formed in the substrate adjacent the gate electrode and sidewall spacers are formed along the sides of the gate electrode including the silicide and the capping layer.Type: GrantFiled: June 7, 1995Date of Patent: October 28, 1997Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Kuei-wu Huang, Tsiu C. Chan, Gregory C. Smith
-
Patent number: 5623438Abstract: A semiconductor read only memory device includes memory cells arranged in a matrix of rows and columns; word lines crossing the matrix, wherein one word line is connected to each row of memory cells; and bit lines interdigitated with column lines and positioned such that each column of memory cells is between a bit line and a column line. The matrix is subdivided into cells, where each cell has four memory cells arranged symmetrically about a bit line in two rows and two columns. All four of the cells are connected to the bit line at a common electrical node, wherein selected cells are connected to a column line. The memory device also includes a row select driver for selecting memory cells in a single row; a column select driver for selecting a single column line; and circuitry for selecting one of the bit lines adjacent to a column line.Type: GrantFiled: August 26, 1996Date of Patent: April 22, 1997Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Elmer H. Guritz, Tsiu C. Chan
-
Patent number: 5595935Abstract: A structure and method for fabricating intergrated circuit which provides for the detection of residual conductive material. A first conductive layer is deposited over the intergrated circuit and patterned to define a first interconnect layer. An insulating layer in then formed over the integrated circuit. A second conductive layer is then deposited and patterned to define a second interconnect layer. Residual conductive material can be formed during pattering of the second interconnect layer when portions of the second conductive layer remain adjacent to the vertical sidewalls of the first interconnect layer. To make the residual conductive material easier to detect, the conductivity of the residual conductive material is increased by either implanting impurities into the integrated circuit or siliciding the residual conductive material with a refractory metal.Type: GrantFiled: April 7, 1995Date of Patent: January 21, 1997Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Tsiu C. Chan, Frank R. Bryant, Lun-Tseng Lu, Che-Chia Wei
-
Patent number: 5525823Abstract: A method for forming field oxide regions on an integrated circuit device includes the steps of providing doped regions for formation of active devices. After the doped regions have been formed, a thick field oxide layer is grown over the entire surface of the device. Field oxide regions are then defined using masking and anisotropic etching steps which provide approximately vertical sidewalls for the field oxide regions, and which do not result in the formation of bird's beaks. Since the active regions are defined prior to formation of the field oxide regions, the active regions extend under the field oxide regions and do not give rise to edge effects.Type: GrantFiled: May 13, 1994Date of Patent: June 11, 1996Assignee: SGS-Thomson Microelectronics, Inc.Inventor: Tsiu C. Chan
-
Patent number: 5500557Abstract: A structure and method for fabricating integrated circuits which provides for the detection of residual conductive material. A first conductive layer is deposited over the integrated circuit and patterned to define a first interconnect layer. An insulating layer is then formed over the integrated circuit. A second conductive layer is then deposited and patterned to define a second interconnect layer. Residual conductive material can be formed during patterning of the second interconnect layer when portions of the second conductive layer remain adjacent to the vertical sidewalls of the first interconnect layer. To make the residual conductive material easier to detect, the conductivity of the residual conductive material is increased by either implanting impurities into the integrated circuit or siliciding the residual conductive material with a refractory metal.Type: GrantFiled: September 24, 1993Date of Patent: March 19, 1996Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Tsiu C. Chan, Frank R. Bryant, Lun-Tseng Lu, Che-Chia Wei
-
Patent number: 5489797Abstract: An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.Type: GrantFiled: April 11, 1995Date of Patent: February 6, 1996Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Tsiu C. Chan, Frank R. Bryant, John L. Walters
-
Patent number: 5478771Abstract: An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.Type: GrantFiled: December 19, 1994Date of Patent: December 26, 1995Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Tsiu C. Chan, Frank R. Bryant, John L. Walters
-
Patent number: 5448091Abstract: A layout and fabrication technique for EPROMs and similar devices includes a preferred technique for partially self-aligning bit line contacts. In addition, a self-aligned, buried Vss line is provided which is in contact with the substrate for its entire length. This provides a highly conductive Vss line, allowing the size of such line to be diminished. The use of a buried Vss contact line and a partially self-aligned bit line contact contributes to a device layout having minimum cell sizes for a given feature size.Type: GrantFiled: September 16, 1994Date of Patent: September 5, 1995Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Frank R. Bryant, Tsiu C. Chan
-
Patent number: 5426065Abstract: An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate transistor has a gate connected to a word line. The SRAM memory cell also includes first and second pull-down transistors configured as a storage latch. The first pull-down transistor has a first source/drain connected to a second source/drain of said first transfer gate transistor; the second pull-down transistor has a first source/drain connected to a second source/drain of said second transfer gate transistor. Both first and second pull-down transistors have a second source/drain connected to a power supply voltage node.Type: GrantFiled: November 30, 1993Date of Patent: June 20, 1995Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Tsiu C. Chan, Frank R. Bryant
-
Patent number: 5377153Abstract: A semiconductor read only memory device includes memory cells arranged in a matrix of rows and columns; word lines crossing the matrix, wherein one word line is connected to each row of memory cells; and bit lines interdigitated with column lines and positioned such that each column of memory cells is between a bit line and a column line. The matrix is subdivided into cells, where each cell has four memory cells arranged symmetrically about a bit line in two rows and two columns. All four of the cells are connected to the bit line at a common electrical node, wherein selected cells are connected to a column line. The memory device also includes a row select driver for selecting memory cells in a single row; a column select driver for selecting a single column line; and circuitry for selecting one of the bit lines adjacent to a column line.Type: GrantFiled: November 30, 1992Date of Patent: December 27, 1994Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Elmer H. Guritz, Tsiu C. Chan
-
Patent number: 5376571Abstract: A layout and fabrication technique for EPROMs and similar devices includes a preferred technique for partially self-aligning bit line contacts. In addition, a self-aligned, buried Vss line is provided which is in contact with the substrate for its entire length. This provides a highly conductive Vss line, allowing the size of such line to be diminished. The use of a buried Vss contact line and a partially self-aligned bit line contact contributes to a device layout having minimum cell sizes for a given feature size.Type: GrantFiled: September 10, 1993Date of Patent: December 27, 1994Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Frank R. Bryant, Tsiu C. Chan
-
Patent number: 5336916Abstract: An integrated circuit structure is suitable for use with SRAM memory devices. P-channel load devices are used in a 6-transistor SRAM cell. The P-channel devices are formed as polycrystalline silicon field effect transistors above the N-channel field effect transistors, which are formed in the substrate. In order to avoid formation of a P-N junction, a barrier layer is formed between P-type and N-type source/drain regions. The preferred barrier is a bilayer formed from a conductive material such as silicide over a doped polycrystalline silicon layer.Type: GrantFiled: July 27, 1992Date of Patent: August 9, 1994Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Tsiu C. Chan, Frank R. Bryant, Lisa K. Jorgenson
-
Patent number: 5330933Abstract: A method for fabricating a resistive load element for a semiconductor device can be used with standard semiconductor processes. A layer of second level poly is deposited and lightly doped P-type. A resist mask is used to dope selected regions of the poly layer N-type. The poly layer is then patterned to define conductors and resistive load elements. The resistive load elements are formed by back-to-back PN diodes formed at the interfaces between the P-type and N-type regions.Type: GrantFiled: July 10, 1992Date of Patent: July 19, 1994Assignee: SGS-Thomson Microelectronics, Inc.Inventors: Tsiu C. Chan, William A. Bishop
-
Patent number: 5329143Abstract: An ESD protection circuit and structure for integrated circuit devices uses a lateral NPN transistor to provide a low resistance discharge path for ESD transient voltages. A preferred structure also includes a modification to an N-channel output drive transistor to eliminate the parasitic bipolar transistor that induces snapback.Type: GrantFiled: December 17, 1992Date of Patent: July 12, 1994Assignee: SGS Thomson Microelectronics, Inc.Inventors: Tsiu C. Chan, David S. Culver