Abstract: A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A conductive layer is formed over a substrate. A silicon nitride layer is formed over the conductive layer. A photoresist layer is then formed and patterned over the silicon nitride layer. The silicon nitride layer and the conductive layer are etched to form an opening exposing a portion of the substrate. The photoresist layer is then removed. The exposed substrate and a portion of the conductive layer exposed along the sidewalls in the opening are oxidized. An planarizing insulating layer such as spin-on-glass is formed over the silicon nitride layer and in the opening. The insulating layer is etched back to expose the silicon nitride wherein an upper surface of the insulating layer is level with an upper surface of the conductive layer. The silicon nitride layer is then removed. A planar silicide layer is then formed over the conductive layer.

Abstract: A structure and method is provided for fabricating an integrated circuit having an N-type well and a P-type well, with the upper surfaces of the N-type well and the P-type well coplanar. An insulating layer is formed over the integrated circuit. A first masking layer is formed over the insulating layer to define locations of a first well to be formed. An impurity of a first conductivity type is implanted into the semiconductor substrate of the integrated circuit to form a first region. The first masking layer is removed, and a second masking layer is formed over the insulating layer to define locations of a second well to be formed. An impurity of a second conductivity type is implanted into the semiconductor substrate of the integrated circuit to form a second region. The second masking layer is then removed. The integrated circuit is thermally heated to form the first and second wells in the substrate.

Abstract: A contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes an ohmic contact with the silicided region of the lower polycrystalline silicon layer.

Abstract: An ESD protection circuit and structure for implementation within an integrated circuit is disclosed. The protection circuit includes a diode, serving as a triggering device, and a lateral bipolar transistor. The triggering voltage of said diode is selected by an implant underlying a first field oxide structure adjacent a first diffused region to which the external terminal is connected. The lateral bipolar transistor uses the first diffused region to which the external terminal is connected as the collector region, a second diffused region opposite the first field oxide structure from said first diffused region as the emitter, and the substrate, or epitaxial layer, as the base. A second field oxide structure encircles the emitter region and has a distance thereacross which is selected in order to provide sufficient base resistance that, upon junction breakdown of the diode, the base-emitter junction of the lateral transistor is forward biased and the transistor turned on.

Abstract: A technique for producing self-aligned contact openings is especially useful when the openings are to be made between conductive structures having relatively small separation. Formation of an oxide layer under particular process conditions results in a thicker layer of oxide on top of the conductive structures, and a thinner oxide layer along the sidewalls and in the bottom of the spacing between them. Deposition of such a differential thickness oxide layer can be followed by an unmasked-anisotropic etch in order to clear the oxide from the space between the conductive structures, without removing all of the oxide layer over the conductive structure. Such a technique can be utilized in integrated circuits such as DRAMs, with the word lines allowing for the formation of semi-self-aligned bit lines. The combination of word lines and bit lines can provide for a fully self-aligned contact opening for DRAM cell capacitors.

Abstract: A method for forming a SRAM structure with polycrystalline P-channel load devices of an integrated circuit, and an integrated circuit formed according to the same, is disclosed. A field oxide region is formed over a portion of the substrate. A first gate electrode of a first N-channel field effect device is formed over the substrate having a source/drain region in the substrate. A second gate electrode of a second N-channel field effect device is also formed over the substrate and a portion of the field oxide. A first insulating layer is formed over the integrated circuit containing an opening exposing a portion of the source/drain region and the second gate electrode of the first and second N-channel devices respectively. An interconnect layer having a doped polysilicon layer and a barrier layer is formed over the integrated circuit, patterned and etched to define a shared contact region covering the exposed source/drain region and the second gate electrode of the N-channel devices.

Abstract: A capacitor suitable for use with a DRAM memory cell is composed of multiple layers of polycrystalline silicon. The storage node is formed from a polycrystalline silicon layer sandwiched between two polysilicon ground plate layers. Such a structure nearly doubles the capacitance for a given chip surface area used. First the bottom polycrystalline silicon plate layer is fabricated, followed by an isolation step and fabrication of the storage node polycrystalline silicon layer. Following another isolation step, the polycrystalline silicon top plate layer is then formed and connected to the bottom plate layer.

Abstract: A method for fabricating a resistive load element for a semiconductor device can be used with standard semiconductor processes. A layer of second level poly is deposited and lightly doped P-type. A resist mask is used to dope selected regions of the poly layer N-type. The poly layer is then patterned to define conductors and resistive load elements. The resistive load elements are formed by back-to-back PN diodes formed at the interfaces between the P-type and N-type regions.

Abstract: A method for forming a SRAM structure with polycrystalline P-channel load devices of an integrated circuit, and an integrated circuit formed according to the same, is disclosed. A first gate electrode of a first N-channel field effect device is formed over the substrate having a source/drain region in the substrate. A second gate electrode of a second N-channel field effect device is also formed over the substrate and a portion of a field oxide. A metal containing layer is formed over the second gate electrode and the source/drain region of the first N-channel device to define a shared contact region. A first conductive layer is formed over the metal containing layer, patterned and etched to define a first and a second gate electrode of a first and a second P-channel field effect device respectively. A second conductive layer is formed over a portion of the first and second P-channel devices, to define a source/drain and channel region of the P-channel devices.

Abstract: A contact structure provides electrical contact between two polycrystalline silicon interconnect layers. The lower layer has a silicide layer on its upper surface. The upper polycrystalline silicon layer can be doped with a different conductivity type, and makes an ohmic contact with the silicided region of the lower polycrystalline silicon layer.

Abstract: A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active area in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SPRAM cells.

Abstract: An N.sup.+ buried layer is formed under all the N-channel devices in the memory array of an integrated circuit device. The N.sup.+ buried layer can also be formed under N-channel input/output devices. The N.sup.+ buried layers include contacts to the power supply. Such a device layout provides for complete isolation of the memory array from the remainder of the circuitry. The isolation of the N-channel input/output devices also provides for enhanced immunity to input/output noise.

Abstract: A capacitor suitable for use with a DRAM memory cell is composed of multiple layers of polycrystalline silicon. The storage node is formed from a polycrystalline silicon layer sandwiched between two polysilicon ground plate layers. Such a structure nearly doubles the capacitance for a given chip surface area used. First the bottom polycrystalline silicon plate layer is fabricated, followed by an isolation step and fabrication of the storage node polycrystalline silicon layer. Following another isolation step, the polycrystalline silicon top plate layer is then formed and connected to the bottom plate layer.

Abstract: A capacitor is formed for use with a DRAM storage cell by lying down alternating layers of polycrystalline silicon for the storage node and the ground plate. A buried bit line allows the capacitor area to cover a significant fraction of the cell layout area. The alternating storage node and ground plates of the capacitor are laid down alternately, and connected together as they are formed. The number of interleaved layers which can be used to form the capacitor can easily be varied to suit process requirements.

Abstract: Field oxide regions are formed between active regions of a silicon substrate by forming over the substrate a sandwich of silicon dioxide, silicon nitride and silicon dioxide layers, opening the layers to expose a portion of the silicon substrate, removing a layer of the exposed substrate, forming side wall spacers on the edges of the opening, removing a layer of the silicon substrate exposed between the side wall spacers, and then reaching the exposed substrate for the thermal oxidation of the exposed substrate for forming the field oxide region. In those structures in which the field oxide is buried in the substrate as shown in FIG. 12, it may be feasible to use thicker field oxide regions and thereby to reduce the need for the heavily doped surface layer under the field oxide.

Abstract: A process for forming electrical interconnect on MOS semiconductor integrated circuits includes the formation of a capping layer of oxide over the first level poly layer prior to patterning. The capping layer is then removed over selected regions. The conductive layer and capping oxide layer are then patterned to form transistor gates and interconnect. Source/drain regions are formed in active areas of the integrated circuit, and sidewall oxide is formed next to the patterned gate regions. When a second layer of interconnect is formed and patterned over the integrated circuit, contact between the first and second interconnect layers is made in the previously defined selected regions.

Abstract: A method of making a trench capacitor employs an N-type switchable plate formed in a P-type substrate for holding charge at either zero volts or a positive TC voltage and a P-type ground plate that fills in a trench around a memory cell, so that P-type dopant diffuses through a thin oxide insulator to form a channel stop and a pinhold short through the oxide is self-healing by the formation of a reverse-biased P-N diode that cuts off the flow of current through the pinhole.

Abstract: A short channel metal oxide semiconductor transistor device is processed without undesirable short channel effects, such as V.sub.T falloff and with a reasonable source-drain operating voltage support. In a substrate lightly doped with P-type conductivity material and source and drain region heavily doped with an N-type conductivity material, two lightly doped N- regions are disposed between the edge of the gate and the source and drain regions. A channel region is more heavily doped with P-type material than the substrate. Two regions extend from opposite sides of the channel region to an area generally below the two N- regions and above the substrate, which regions are more heavily doped than the channel regions.

Abstract: A method for making a semiconductor device is described in which overlapping polycrystalline silicon layers are deposited over selected portions of a semiconductor substrate and insulated from the substrate and from each other, thereby providing an improved semiconductor device for use in a random-access memory integrated circuit.

Abstract: A short channel metal oxide semiconductor transistor device is processed without undesirable short channel effects, such as V.sub.T falloff and with a reasonable source-drain operating voltage support. In a substrate lightly doped with P-type conductivity material and source and drain region heavily doped with an N-type conductivity material, two lightly doped N- regions are disposed between the edge of the gate and the source and drain regions. A channel region is more heavily doped with P-type material than the substrate. Two regions extend from opposite sides of the channel region to an area generally below the two N- regions and above the substrate, which regions are more heavily doped than the channel regions.