Patents by Inventor Tsu-Jae King

Tsu-Jae King has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Two terminal silicon based negative differential resistance device
    Patent number: 7016224
    Abstract: A two terminal, silicon based negative differential resistance (NDR) element is disclosed, to effectuate a type of NDR diode for selected applications. The two terminal device is based on a three terminal NDR-capable FET which has a modified channel doping profile, and in which the gate is tied to the drain. This device can be integrated through conventional CMOS processing with other NDR and non-NDR elements, including NDR capable FETs. A memory cell using such NDR two terminal element and an NDR three terminal is also disclosed.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: March 21, 2006
    Inventor: Tsu-Jae King
  • Integrated circuit having negative differential resistance (NDR) devices with varied peak-to-valley ratios (PVRs)
    Patent number: 7012833
    Abstract: An integrated circuit is disclosed which includes a variety of NDR devices having different characteristics. The different NDR devices are formed to have different PVRs, different onset NDR voltages, etc. in a common substrate, by controlling various conventional processing operations, such as an implant, an anneal, an insulator film deposition, and the like.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: March 14, 2006
    Assignee: Progressant Technologies, Inc.
    Inventor: Tsu-Jae King
  • Enhanced read and write methods for negative differential resistance (NDR) based memory device
    Patent number: 7012842
    Abstract: An enhanced method of writing and reading a memory device, such as an SRAM using negative differential resistance (NDR) elements), is disclosed. This is done through selective control of biasing of the active elements in a memory cell. For example in a write operation, a memory cell is placed in an intermediate state to increase write speed. In an NDR based embodiments, this is done by reducing a bias voltage to NDR FETs so as to weaken the NDR element (and thus disable an NDR effect) during the write operation. Conversely, during a read operation, the bias voltages are increased to enhance peak current (as well as an NDR effect), and thus provide additional current drive to a BIT line. Embodiments using such procedures achieve superior peak to valley current ratios (PVR), read/write speed, etc.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: March 14, 2006
    Assignee: Progressant Technologies, Inc.
    Inventor: Tsu-Jae King
  • N-channel pull-up element and logic circuit
    Patent number: 7005711
    Abstract: An n-channel field effect transistor (FET) includes a switchable negative differential resistance (SNDR) characteristic. The n-channel SNDR FET is configured as a depletion mode device, and biased so that it operates essentially as a p-channel device. The device is suitable as a replacement for a p-channel pull-up devices in logic gates (including in inverters) and memory cells.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: February 28, 2006
    Assignee: Progressant Technologies, Inc.
    Inventor: Tsu-Jae King
  • Variable voltage supply bias and methods for negative differential resistance (NDR) based memory device
    Publication number: 20060028881
    Abstract: Static random access memory (SRAM) performance is enhanced through the use of appropriate latch strength control. For example, latch strength in an SRAM cell is increased during data store operations to reduce power dissipation and improve reliability. Latch strength can also be increased to improve read speed, while latch strength can be reduced to improve write speed. In an SRAM cell including at least a negative differential resistance (NDR) device as a pull-up element, this type of latch control can be achieved through appropriate biasing of the NDR device(s). For example, drain-to-source bias can be increased or decreased to increase or decrease, respectively, latch strength. Similarly, gate-to-source bias can be increased or decreased to increase or decrease, respectively, latch strength.
    Type: Application
    Filed: October 3, 2005
    Publication date: February 9, 2006
    Applicant: Progressant Technologies, Inc.
    Inventor: Tsu-Jae King
  • Method of making memory cell utilizing negative differential resistance devices
    Patent number: 6990016
    Abstract: A two terminal, silicon based negative differential resistance (NDR) element is disclosed, to effectuate of NDR diode for selected applications. The two terminal device is based on a three terminal NDR-capable FET which has a modified channel doping profile, and in which the gate is tied to the drain. This device can be integrated through conventional CMOS processing with other NDR and non-NDR elements, including NDR capable FETs. A memory cell using such NDR two terminal element and an NDR three terminal is also disclosed.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: January 24, 2006
    Assignee: Progressant Technologies, Inc.
    Inventor: Tsu-Jae King
  • Negative differential resistance (NDR) elements and memory device using the same
    Publication number: 20060007773
    Abstract: A two-terminal NDR device can be formed by coupling the gate and drain of an NDR-capable FET, such that the coupled gate and drain form a first terminal and the source of the NDR-capable FET forms the second terminal. By applying an appropriate body bias between the body and source of an NDR-capable FET configured in this manner, the NDR-capable FET can be forced to operate with a negative threshold voltage, thereby allowing the resulting two-terminal device to exhibit the desired NDR characteristics. This two-terminal device can, for example, be used as a load element in a static random access memory (SRAM) cell and various other circuits where the NDR behavior of the device would be beneficial.
    Type: Application
    Filed: September 15, 2005
    Publication date: January 12, 2006
    Applicant: Progressant Technologies, Inc.
    Inventor: Tsu-Jae King
  • Process for controlling performance characteristics of a negative differential resistance (NDR) device
    Patent number: 6979580
    Abstract: A variety of processes are disclosed for controlling NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters. The processes are based on conventional semiconductor manufacturing operations so that an NDR device can be fabricated using silicon based substrates and along with other types of devices.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: December 27, 2005
    Assignee: Progressant Technologies, Inc.
    Inventor: Tsu-Jae King
  • Method of forming a negative differential resistance device
    Patent number: 6980467
    Abstract: A negative differential resistance (NDR) field-effect transistor element is disclosed, formed on a silicon-based substrate using conventional MOS manufacturing operations. Methods for improving a variety of NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters are also disclosed.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: December 27, 2005
    Assignee: Progressant Technologies, Inc.
    Inventor: Tsu-Jae King
  • Negative differential resistance pull up element for DRAM
    Publication number: 20050269628
    Abstract: A memory cell includes a pull-up element that exhibits a refresh behavior that is dependent on the data value stored in the memory cell. The pull-up element is an NDR FET connected between a high voltage source and a storage node of the memory cell. The NDR FET receives a pulsed gate bias signal, wherein each pulse turns on the NDR FET when a logic HIGH value is stored at the storage node, and further wherein each pulse does not turn on the NDR FET when a logic LOW value is stored at the storage node. In this fashion a DRAM cell (and device) can be operated without a separate refresh cycle.
    Type: Application
    Filed: August 8, 2005
    Publication date: December 8, 2005
    Applicant: Progressant Technologies, Inc.
    Inventor: Tsu-Jae King
  • CMOS process compatible, tunable negative differential resistance (NDR) device and method of operating same
    Patent number: 6972465
    Abstract: A CMOS based n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits a useful negative differential resistance effect is disclosed. The resulting device can be incorporated into a number of useful applications, including as part of a memory device, a logic device, etc.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: December 6, 2005
    Assignee: Progressant Technologies, Inc.
    Inventors: Tsu-Jae King, David K. Y. Liu
  • Variable threshold semiconductor device and method of operating same
    Patent number: 6969894
    Abstract: An n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits a variable threshold voltage is disclosed. The resulting device can be incorporated into a number of useful applications, including as part of a memory device, a logic device, etc.
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: November 29, 2005
    Assignee: Synopsys, Inc.
    Inventors: Tsu-Jae King, David K. Y. Liu
  • Method of forming a negative differential resistance device
    Publication number: 20050260798
    Abstract: A negative differential resistance (NDR) field-effect transistor element is disclosed, formed on a silicon-based substrate using conventional MOS manufacturing operations. Methods for improving a variety of NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters are also disclosed.
    Type: Application
    Filed: January 28, 2005
    Publication date: November 24, 2005
    Applicant: Progressant Technologies, Inc.
    Inventor: Tsu-Jae King
  • Method of forming a negative differential resistance device
    Publication number: 20050253133
    Abstract: A negative differential resistance (NDR) field-effect transistor element is disclosed, formed on a silicon-based substrate using conventional MOS manufacturing operations. Methods for improving a variety of NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters are also disclosed.
    Type: Application
    Filed: January 28, 2005
    Publication date: November 17, 2005
    Applicant: Progressant Technologies, Inc.
    Inventor: Tsu-Jae King
  • Damascene process for use in fabricating semiconductor structures having micro/nano gaps
    Publication number: 20050250236
    Abstract: In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.
    Type: Application
    Filed: May 3, 2005
    Publication date: November 10, 2005
    Inventors: Hideki Takeuchi, Emmanuel Quevy, Tsu-Jae King, Roger Howe
  • Two bit/four bit SONOS flash memory cell
    Publication number: 20050242391
    Abstract: Charge migration in a SONOS memory cell is eliminated by physically separating nitride layer storage sites with dielectric material. Increased storage in a cell is realized with a double gate structure for controlling bit storage in line channels between a source and a drain, such as with a FinFET structure in which the gates are folded over the channels on sides of a fin.
    Type: Application
    Filed: May 2, 2005
    Publication date: November 3, 2005
    Inventors: Min She, Tsu-Jae King
  • Negative differential resistance load element
    Patent number: 6933548
    Abstract: A negative differential resistance device is disclosed which is particularly suited as a replacement in memory cells for conventional pull-up and load elements such as NDR diodes, passive resistors, and conventional FETs. The NDR device includes a charge trapping layer formed at or extremely near to an interface between a substrate (which can be silicon or SOI) and a gate insulation layer. The NDR device can be shut off during static operations to further reduce power dissipation.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: August 23, 2005
    Assignee: Synopsys, Inc.
    Inventor: Tsu-Jae King
  • Flash memory devices using large electron affinity material for charge trapping
    Publication number: 20050167734
    Abstract: Disclosed is a novel flash memory device using a high-permittivity dielectric such as HfO2 or TiO2 as a charge trapping layer. Numerical simulation shows that the novel trapping material will enhance the retention time/programming speed ratio by 5 orders of magnitude, compared to the conventional Si3N4 trapping layer. Capacitors with HfO2 deposited by RTCVD as the charge trap/storage layer in SONOS-type flash memory devices were fabricated and characterized. Compared against devices with Si3N4 trapping layer, faster programming speed as well as good retention time is achieved with low programming voltage.
    Type: Application
    Filed: November 19, 2004
    Publication date: August 4, 2005
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Min She, Tsu-Jae King
  • Charge trapping device and method of forming the same
    Publication number: 20050156158
    Abstract: A charge trapping device, and a method of forming the same is disclosed. Charge traps are optimally distributed through a trapping region based on controlling various conventional processing operations, such as an implant, an anneal, an insulator film deposition, and the like. In some embodiments, FETs can be configured to include a negative differential resistance (NDR) characteristic when they utilize a particular charge trap energy and distribution.
    Type: Application
    Filed: November 4, 2004
    Publication date: July 21, 2005
    Inventor: Tsu-Jae King
  • Process for controlling performance characteristics of a negative differential resistance (NDR) device
    Publication number: 20050153461
    Abstract: A variety of processes are disclosed for controlling NDR characteristics for an NDR element, such as peak-to-valley ratio (PVR), NDR onset voltage (VNDR) and related parameters. The processes are based on conventional semiconductor manufacturing operations so that an NDR device can be fabricated using silicon based substrates and along with other types of devices.
    Type: Application
    Filed: November 4, 2004
    Publication date: July 14, 2005
    Applicant: Progressant Technologies, Inc.
    Inventor: Tsu-Jae King