Abstract: In the channel layer of a thin film transistor (TFT), a channel and its drain meet at a transition within a transition region. The channel extends in a first, or horizontal, dimension away from the drain and extends in a second, or vertical, dimension from a side away from the gate to a side toward the gate. The charge carrier densities in the transition region vary in the second dimension in a way that reduces leakage current, because the position of the maximum electric field is moved away from the gate and its magnitude is reduced. Variation of densities in the second dimension can be produced by high angle implantation of a dopant and a counterdopant, providing a transition region between the drain and the channel underneath the gate.

Abstract: MOS transistors are formed in thin films of Ge/Si alloys (Ge.sub.x Si.sub.1-x). According to the process of the present invention, polycrystalline films of Ge/Si are deposited using commercially-available LPCVD equipment, which in the preferred process uses silane and germane as the sources of Ge and Si. The deposited Ge.sub.x Si.sub.1-x films are polycrystalline at temperatures for processing down to as below 400.degree. C., and the films can be doped heavily by ion implantation and annealing at temperatures as low as 600.degree. C. to give high mobility and dopant activation yielding very low resistivity. By carrying out the annealing step in the formation of the thin film transistors in the temperature range of 400.degree. to 500.degree. C., the films provide very large grain size, minimizing the impact of grain boundaries in the polycrystalline films where the thin film transistors are to be formed. As a result, thin film MOS transistors are fabricated at temperatures below 500.degree. C.