Abstract: A semiconductor manufacturing process is disclosed that is suitable for making both negative differential resistance (NDR) and non-NDR devices at the same time. An NDR process is thus integrated within a conventional CMOS process so that compatibility with existing fabrication procedures is maintained. In addition, many of the NDR process steps and non-NDR process steps are shared in common to form features of such devices at the same time.

Abstract: A silicon-on-insulator (SOI) memory device (such as an SRAM) using negative differential resistance (NDR) elements is disclosed. Body effect performances for NDR FETs (and other FETs) that may be used in such device are enhanced by floating a body of some/all the NDR FETs.

Abstract: An enhanced method of writing and reading a memory device, such as an SRAM using negative differential resistance (NDR) elements), is disclosed. This is done through selective control of biasing of the active elements in a memory cell. For example in a write operation, a memory cell is placed in an intermediate state to increase write speed. In an NDR based embodiments, this is done by reducing a bias voltage to NDR FETs so as to weaken the NDR element (and thus disable an NDR effect) during the write operation. Conversely, during a read operation, the bias voltages are increased to enhance peak current (as well as an NDR effect), and thus provide additional current drive to a BIT line. Embodiments using such procedures achieve superior peak to valley current ratios (PVR), read/write speed, etc.

Abstract: A two terminal, silicon based negative differential resistance (NDR) element is disclosed, to effectuate a type of NDR diode for selected applications. The two terminal device is based on a three terminal NDR-capable FET which has a modified channel doping profile, and in which the gate is tied to the drain. This device can be integrated through conventional CMOS processing with other NDR and non-NDR elements, including NDR capable FETs. A memory cell using such NDR two terminal element and an NDR three terminal is also disclosed.

Abstract: A process for operating a dual mode FET and a logic circuit to include a negative differential resistance (NDR) characteristic is disclosed. In a FET embodiment, an NDR characteristic is selectively enabled/disabled by biasing a body contact, thus permitting a dual behavior of the device. Larger collections of such FETs can be synthesized to form dual mode logic circuits as well, so that a single circuit can perform more than one logic operation depending on whether an NDR mode is enabled or not.

Abstract: A gate structure for a MOSFET device comprises a gate insulation layer, a first layer of a first metal abutting the gate insulation layer, and a second layer overlying the first layer and comprising a mixture of the metal of the first layer and a second metal, the metal layers formed by the diffusion of the first metal into and through the second metal. The second metal can be used as the gate for a n-MOS transistor, and the mixture of first metal and second metal overlying a layer of the first metal can be used as a gate for a p-MOS transistor where the first metal has a work function of about 5.2 eV and the second metal has a work function of about 4.1 eV.

Abstract: An extractor system for a plasma ion source has a single (first) electrode with one or more apertures, or a pair of spaced electrodes, a first or plasma forming electrode and a second or extraction electrode, with one or more aligned apertures. The aperture(s) in the first electrode (or the second electrode or both) have a counterbore on the downstream side (i.e. away from the plasma ion source or facing the second electrode). The counterbored extraction system reduces aberrations and improves focusing. The invention also includes an ion source with the counterbored extraction system, and a method of improving focusing in an extraction system by providing a counterbore.

Abstract: A method of making an n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits negative differential resistance in its output characteristic (drain current as a function of drain voltage) is disclosed. By implanting ions into a substrate that is later thermally oxidized, a number of temporary charge trapping sites can be established above a channel region of a transistor. The channel is also heavily doped, so that a strong electrical field can be generated to accelerate hot carriers into the temporary charge trapping sites. The insulating layer formed during the oxidation step is made sufficiently thick to prevent quantum tunnelingo of the hot carriers into a gate electrode. Other suitable and conventional processing steps are used to finalize completion of the fabrication of the NDR device so that the entire process is compatible and achieved with CMOS processing techniques.

Abstract: An active negative differential resistance element (an NDR FET) and a memory device (such as an SRAM) using such elements is disclosed. Soft error rate (SER) performance for NDR FETs and such memory devices are enhanced by adjusting a location of charge traps in a charge trapping layer that is responsible for effectuating an NDR behavior. Both an SER and a switching speed performance characteristic can be tailored by suitable placement of the charge traps.

Abstract: An electronic device includes a FET that is capable of operating in a negative differential resistance mode as well as in a conventional FET mode. The selection of the mode can be accomplished by providing a control signal to a body terminal of the FET as needed for a particular application. By providing two different operating modes a multi-function logic gate is effectuated that can perform two or more different logical functions on an input signal. Furthermore the device can be used as an element of a new logic family and synthesized into suitable configurations so that more sophisticated and complex functions are achieved with increased density, lower power, etc. over conventional semiconductor FETs.

Abstract: An n-channel metal-insulator-semiconductor field-effect transistor (MISFET) that exhibits negative differential resistance in its output characteristic (drain current as a function of drain voltage) is disclosed. For a fixed gate voltage, the MISFET channel current, which flows between the drain and source terminals of the transistor, firstly increases as the drain-to-source voltage increases above zero Volts. Once the drain-to-source voltage reaches a pre-determined level, the current subsequently decreases with increasing drain-to-source voltage. In this region of operation, the device exhibits negative differential resistance, as the drain current decreases with increasing drain voltage. The drain-to-source voltage corresponding to the onset of negative differential resistance is also tunable. In addition, the drain current and negative differential resistance can be electronically tailored by adjusting the gate voltage.

Abstract: A charge trapping structure for use with an n-channel metal-insulator-semiconductor field-effect transistor (MISFET) is disclosed. A dielectric layer is formed close to a channel region of the MISFET, and includes a number of trapping sites which are arranged and have a concentration sufficient to temporarily store energetic electrons induced by an electric field to move from the channel into the trapping sites. The trapped electrons set up a counter field that depletes the channel of carriers, and as a bias voltage across the channel increases, the device exhibits negative differential resistance (NDR). The charge trapping structure, as well as the rest of the device, are formed using conventional CMOS processing techniques.

Abstract: This invention relates to micro-electromechanical systems using silicon-germanium films. Such a system includes one or more layers of Si1−xGex, deposited on a substrate, where 0<x≦1. One or more transistors can be formed on the substrate.

Abstract: A FinFET device is fabricated using conventional planar MOSFET technology. The device is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layer as a fin. Double gates are provided over the sides of the channel to provide enhanced drive current and effectively suppress short channel effects. A plurality of channels can be provided between a source and a drain for increased current capacity. In one embodiment two transistors can be stacked in a fin to provide a CMOS transistor pair having a shared gate.

Abstract: An electronic device includes a FET that is capable of operating in a negative differential resistance mode as well as in a conventional FET mode. The selection of the mode can be accomplished by providing a control signal to a body terminal of the FET as needed for a particular application. By providing two different operating modes a multi-function logic gate is effectuated that can perform two or more different logical functions on an input signal. Furthermore the device can be used as an element of a new logic family and synthesized into suitable configurations so that more sophisticated and complex functions are achieved with increased density, lower power, etc. over conventional semiconductor FETs.

Abstract: A memory cell using both negative differential resistance (NDR) and conventional FETs is disclosed. A pair of NDR FETs are coupled in a latch configuration so that a data value passed by a transfer FET can be stored at a storage node. By exploiting an NDR characteristic, the memory cell can be implemented with fewer active devices. Moreover, an NDR FET can be manufactured using conventional MOS processing steps so that process integration issues are minimized as compared to conventional NDR techniques.

Abstract: A semiconductor device is disclosed that includes integrated insulated-gate field-effect transistor (IGFET) elements and one or more negative differential resistance (NDR) field-effect transistor elements, combined and formed on a common substrate. Thus, a variety of circuits, including logic and memory are implemented with a combination of conventional and NDR capable FETs. Because both types of elements share a number of common features, they can be fabricated with common processing operations to achieve better integration in a manufacturing facility.

Abstract: This invention relates to micro-electromechanical systems using silicon-germanium films.

Abstract: A new process to form a polycrystalline silicon film using a polycrystalline silicon-germanium (poly-Si.sub.1-x Ge.sub.x) capping film to "seed" crystallization of an amorphous silicon film on an upper surface of a substrate. The polycrystalline silicon film has no nucleation sites and a greater number of grain boundaries in the region near the polycrystalline silicon upper surface than in the region near the polycrystalline silicon and substrate upper surface interface. This indicates that crystallization and crystal growth occurred from the polycrystalline silicon upper surface and proceeded in a direction towards the substrate upper surface.

Abstract: A new polycrystalline silicon film which has been crystallized using a polycrystalline silicon-germanium (poly-Si.sub.1-x Ge.sub.x) capping film to "seed" crystallization of an amorphous silicon film on an upper surface of a substrate. The polycrystalline silicon film has no nucleation sites and a greater number of grain boundaries in the region near the polycrystalline silicon upper surface than in the region near the polycrystalline silicon and substrate upper surface interface. This indicates that crystallization and crystal growth occurred from the polycrystalline silicon upper surface and proceeded in a direction towards the substrate upper surface.