Abstract: A memory cell array has a plurality of memory cells and dummy memory cells. A column select portion switches access control to a memory cell in accordance with a mode control signal. The column select portion selects one memory cell column to connect a first or second bit line connected with one selected memory cell and first and second reference data lines connected with the dummy memory cells to a data read circuit in a first mode. The column select portion connects the first and second bit lines respectively connected to paired two selected memory cells storing data complimentary to each other to the data read circuit in a second mode.

Abstract: A tunneling magneto-resistance element forming an MTJ memory cell is connected between a bit line and a strap. In each memory cell column, the strap is shared by the plurality of tunneling magneto-resistance elements in the same row block. The access transistor is connected between strap and ground voltage, and is turned on/off in response to a corresponding word line. Storage data is read from the selected memory cell based on a comparison between results of data reading effected on a memory cell group coupled to the same strap before and after application of a predetermined magnetic field to the selected memory cell.

Abstract: During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is completed early so that it is possible to reduce a time required from start of the data reading to such a state that a passing current difference between the data lines reaches a level corresponding to storage data of the selected memory cell, and the data reading can be performed fast.

Abstract: For writing K-bit write data in parallel (K is integer at least 2), bit lines each arranged for each memory cell columns and at least K current return lines are provided. K selected bit lines to write the K-bit write data are connected in series in a single current path. When data having different levels are written through adjacent selected bit lines, the selected bit lines are connected to each other at their one ends or the other ends, so that a bit line write current flowing through the former selected bit line is directly transmitted to the latter selected bit line. On the other hand, when data having the same level are written through adjacent selected bit lines, a bit line write current flowing through the former selected bit line is turned back by the corresponding current return line, and then transmitted to the latter selected bit line.

Abstract: Peripheral circuitry writes/reads input data and output data of L bits (L: integer of at least 2) that is input/output to/from a data node into/from first and second memory cell blocks that are selectively accessed. The peripheral circuitry uses circuit components operating in response to a clock signal to write/read the data by dividing the data writing operation/data reading operation into a plurality of stages and carrying out them in pipelining manner.

Abstract: In order to reduce a gate-source leakage current in a standby state, the gate insulating film of one of transistors in each of inverters IV1-IV5 is made thick. In a standby state, an input signal IN has L level and accordingly one of the transistors in inverters IV1-IV5 each that is connected to a main power supply line or a main ground line is turned on. The turned-on transistors have the gate insulating film which is made thicker than that of normal transistors to reduce the gate leakage current thereby reduce current consumption in the standby state.

Abstract: A thin film magnetic memory device includes: a TMR element, provided on a main surface of a silicon substrate, operating as a memory element; a buffer layer having a first surface bringing into contact with the TMR element and a second surface, located on the side opposite to the first surface, having an area smaller than that of the first surface; and a bit line, formed of a conductor film and a barrier metal film that bring into contact with the second surface, extending in one direction so as to intersect the TMR element. Thereby, it is possible to provide a thin film magnetic memory device realizing miniaturization of the memory cell and, also, having a high reliability, and a manufacturing method therefor.

Abstract: A semiconductor memory device includes an address register circuit for storing a plurality of address signals when an address latch enable signal is active in synchronization with a basic timing signal. When an internal operation start instructing signal is activated, a selected address signal from the address register circuit is supplied to a row decoder and a column decoder for memory cell selection. While an internal memory selection operation is performed, an address signal is stored in the address register circuit. Application of an address signal and a memory accessing is carried out asynchronously.

Abstract: A thin film magnetic memory device includes: TMR elements provided at a predetermined distance away from each other on a main surface of a silicon substrate so as to operate as memory elements; a first digit line for applying a magnetic field to TMR element, extending in one direction so as to intersect TMR element; a second digit line for applying a magnetic field to TMR element, extending parallel to the first digit line so as to intersect TMR element; and a magnetic film provided so as to fill in the space between the first digit line and the second digit line and so as to bring into contact with the first and second digit lines. The present invention provides a thin film magnetic memory device wherein crosstalk can be prevented from generating between adjacent memory cells and wherein wire resistance does not increase.

Abstract: In a sense amplifier, local I/O lines are maintained at a predetermined voltage by transistors. Transistors forming a current mirror supply an operating current according to a passing current which flows through transistors, to sense nodes. Transistors forming a current mirror extract an operating current according to the passing current which flows through transistors, from sense nodes. As a result, a voltage difference is generated in sense nodes in accordance with the operating current difference.

Abstract: A switch section for changing the function of an FPGA is provided with a data latch circuit used for connection control. The data latch circuit includes program sections in which program data is stored in advance, and latch unit. At the time of changing the function, control signals are selectively inputted, whereby latch unit and program section are electrically coupled to each other, and a data signal stored in program section is outputted from the data latch circuit. With this arrangement, it is possible to easily change the function of an FPGA without rewriting program data.

Abstract: A tunneling magneto-resistance element of each MTJ (magnetic tunnel junction) memory cell is connected between a bit line and a strap. Each strap is shared by a plurality of tunneling magneto-resistance elements that are located adjacent to each other in the row direction in the same sub array. Each access transistor is connected between a corresponding strap and a ground voltage, and turned ON/OFF in response to a corresponding word line. Since data read operation can be conducted with the structure that does not have an access transistor for every tunneling magneto-resistance element, the array area can be reduced.

Abstract: In a read operation, for example, 32 sense amplifiers read 32 pieces of data in a group. After that, the read data is outputted on a 4-bit unit basis. A memory cell array operates at a low frequency which is ⅛ of an actual data output frequency. On the other hand, in a write operation, data is transferred from the outside to a semiconductor memory device bit by bit every cycle. Consequently, by providing a number of latches of a pipeline in a write access path, the writing operation is enabled even at a high frequency. Specifically, at the time of reading, a memory array operates at a low frequency which is ⅛ of a data output frequency. At the time of writing, data is written every clock. Therefore, a nonvolatile semiconductor memory device which can be programmed at a high transfer speed can be provided. The present invention is particularly effective to a memory cell to which data can be written at high speed like an MRAM.

Abstract: A first feature of a data processing system is in that, in a data transfer path including a plurality of signal lines used for data transfer, a phase control is performed independently for each of the signal lines. A second feature is in that data is selectively transferred from a coupling exchange to a signal processor or a signal memory. A third feature is in that the signal processor, the signal memory and the coupling exchange are coupled to each other. By the features, the phase margin in the transfer data and clocks is widened and high speed transfer can be realized. Since data can be directly written in the signal memory, the signal processor can be efficiently used. Further, efficiency in processing and transfer of signals is improved.

Abstract: A test mode control circuit detects designation of a test mode in accordance with a combination of external control signals and address signals, and activates an internal period setting circuit. Internal period setting circuit generates a clock signal having a prescribed period when activated, and applies it to a control circuit. In accordance with the test mode designating signal from test mode setting circuit and the clock signal from internal period setting circuit, control circuit causes an internal address generating circuit to generate an internal address signal successively in synchronization with the clock signal, so that a word line of a memory array is selected.

Abstract: A semiconductor memory device uses memory cells, which have structures not increasing areas, and are arranged in a distinctive manner providing high data holding stability.

Abstract: A memory block is divided into block units for which parallel data write is performed. Current supply sections capable of supplying a power supply voltage and a ground voltage are provided for block units, independently of one another. With this configuration, in each block unit, writing of data to a selected memory cell is performed by a data write current from the independent current supply section connected to the power supply voltage and the ground voltage. That is, wiring lengths of power supply lines for supplying the power supply voltage and the ground voltage can be shortened. It is therefore possible to suppress a wiring resistance of the power supply line and to supply a desired data write current.

Abstract: In this MRAM device, a memory block is divided into 4 regions, and 4 constant current circuits are respectively provided corresponding to the 4 regions. Bit line drivers select 2 bit lines from each of the 4 regions, that is, 8 bit lines are selected. Bit line drivers supply, to each bit line, an output current from the constant current circuit corresponding to that bit line. Accordingly, a write current flowing through a bit line can be stabilized, and stable data writing can be achieved.

Abstract: When a non-volatile memory cell which can store two bits per one memory cell and pass current bidirectionally is used, a bias power source potential is provided also to a bit line BL4 adjacent to two bit lines (BL2 and BL2) passing a sense current BL2 and BL3. Switch units are provided corresponding to each bit line for selectively connect to any one of a ground power source line, read power source line or bias power source line. The current flowing from a sense amplifier circuit to the adjacent bit line BL4 via adjacent memory cell can be reduced, and thus the current in the sense amplifier circuit is stabilized quickly. Accordingly, a non-volatile semiconductor memory device allows high-speed data reading operation.

Abstract: An operating current is supplied from a power supply node to an internal circuit. In a test mode, current supply from a power supply to the power supply node is stopped by a current switch, and an externally adjustable test current is supplied to the power supply node. The test current is set in accordance with an acceptable value of a leakage current in the internal circuit. Evaluation is made as to whether the leakage current in the internal circuit is not greater than the acceptable value, in accordance with an output of a voltage comparison circuit detecting a voltage drop at the power supply node.