Patents by Inventor Tsukasa Ooishi

Tsukasa Ooishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device
    Patent number: 6646907
    Abstract: A semiconductor memory device uses memory cells, which have structures not increasing areas, and are arranged in a distinctive manner providing high data holding stability. A semiconductor memory device includes memory cells formed on a main surface of a semiconductor substrate, and each having first and second transistors each having a gate electrode and impurity regions forming source/drain as well as one capacitor; and bit and word lines for controlling an operation of the memory cells, a cell plate forming an electrode of the capacitor being formed of the same layer as the gate electrode.
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: November 11, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tsukasa Ooishi
  • Navigation system for transmitting real-time information allowing instant judgement of next action
    Patent number: 6643581
    Abstract: A server receives real-time information indicating a ground road traffic state and the like from a satellite or a camera at certain time intervals, and updates and records the real-time information in a database. If receiving positional information such as a present position from a navigator of a client, the server determines an information extraction range based on the positional information, extracts real-time information falling within the determined information extraction range from the database and transmits the extracted real-time information to the navigator through a satellite communication network. A main body unit of the navigator receives the real-time information and the navigator displays the received real-time information on a display unit. As a result, the present invention can transmit real-time information allowing a client to instantly judge a next action while moving by vehicle.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: November 4, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tsukasa Ooishi
  • Thin film magnetic memory device reducing a charging time of a data line in a data read operation
    Publication number: 20030198081
    Abstract: During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is completed early so that it is possible to reduce a time required from start of the data reading to such a state that a passing current difference between the data lines reaches a level corresponding to storage data of the selected memory cell, and the data reading can be performed fast.
    Type: Application
    Filed: September 30, 2002
    Publication date: October 23, 2003
    Applicants: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Company Limited
    Inventors: Hiroaki Tanizaki, Hideto Hidaka, Tsukasa Ooishi
  • Internal clock generating circuit for clock synchronous semiconductor memory device
    Patent number: 6636110
    Abstract: To input buffers included in a peripheral pad group inputting an external signal and a DQ pad group for data input/output, clock signals from a synchronizing circuit are transmitted through a clock distributing circuit having a plurality of clock transmission nodes arranged in a shape of a tree. The synchronizing circuit accomplishes phase synchronization between a signal from a node nearest to the clock distributing circuit with an external clock signal. Thus, a skew in clock signals applied to the input and output buffers can be eliminated.
    Type: Grant
    Filed: April 28, 1999
    Date of Patent: October 21, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tsukasa Ooishi, Narumi Sakashita
  • Thin film magnetic memory device provided with a dummy cell for data read reference
    Publication number: 20030189853
    Abstract: Normal memory cells and dummy cells are arranged continuously in a memory array. In a data read operation, first and second data lines are connected to the selected memory cell and the dummy cell, respectively, and are supplied with operation currents of a differential amplifier. An offset corresponding to a voltage difference between first and second offset control voltages applied from voltage generating circuits are provided between passing currents of the first and second data lines, and a reference current passing through the dummy cell is set to a level intermediate between two kinds of levels corresponding to storage data of a data read current passing through the selected memory cell.
    Type: Application
    Filed: October 1, 2002
    Publication date: October 9, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Company Limited
    Inventors: Hiroaki Tanizaki, Hideto Hidaka, Takaharu Tsuji, Tsukasa Ooishi
  • Semiconductor memory device having potential control circuit
    Publication number: 20030174570
    Abstract: If data is to be written to a specific memory cell in each of two adjacent memory cell array blocks, a switch control circuit and a supply circuit supply a first predetermined potential to a first bit line out of first and second bit lines connected to the specific memory cell and supply a second predetermined potential to the second bit line in one memory cell array block. In addition, the first predetermined potential is supplied to the second bit line and the second predetermined potential is supplied to the first bit line in the other memory cell array block. Due to this, this semiconductor memory device can improve throughput while suppressing a current which unnecessarily occurs during data write.
    Type: Application
    Filed: August 19, 2002
    Publication date: September 18, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tsukasa Ooishi
  • Random logic circuit
    Patent number: 6621306
    Abstract: A random logic circuit comprises an input portion for inputting data; a first latch portion for receiving the data outputted from the input portion, and holding and outputting the data; a second latch portion for receiving the data outputted from the first latch portion, and holding and outputting the data; an output portion for receiving the data outputted from the second latch portion and outputting the data to a logic circuit; and a prevention circuit for preventing generation of a sub-threshold leak current in sleep mode between the first latch portion and the second latch portion.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: September 16, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tsukasa Ooishi, Hideto Hidaka
  • Semiconductor memory device
    Publication number: 20030169622
    Abstract: A plurality of sense amplifiers are connected to a selected bit line. Each sense amplifier is supplied with a residual current corresponding to a current flowing in a memory cell and a reference current serving as a reference for a threshold voltage of the memory cell to sense the currents. Operations of the sense amplifiers are controlled such that different sense margins are provided to different sense amplifiers and a margin failure is detected according to coincidence/non-coincidence in logical level between output signals of the sense amplifiers. The address of a memory cell with the margin failure is registered. With such a construction, a threshold voltage defect of a non-volatile memory cell is compensated for to enable internal reading of memory cell data with correctness.
    Type: Application
    Filed: December 23, 2002
    Publication date: September 11, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Tsukasa Ooishi, Jun Ohtani, Hiroshi Kato
  • Non-volatile semiconductor memory device with a memory array preventing generation of a through current path
    Patent number: 6618286
    Abstract: A NROM(R) memory array is divided into memory blocks. An isolating portion for electrically isolating corresponding memory blocks from each other is formed in the boundary region between adjacent memory blocks. When read or write operation is performed one bit per memory block, a through current path can be prevented from being generated in the read or write operation.
    Type: Grant
    Filed: May 16, 2002
    Date of Patent: September 9, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Kato, Tsukasa Ooishi
  • Write system architecture of magnetic memory array divided into a plurality of memory blocks
    Patent number: 6618317
    Abstract: During data write, a first driver electrically connects a fist shared node to one of first and second voltages in accordance with write data. A second driver electrically connects a second shared node to the other voltage. A plurality of first switch circuits for electrically connecting one end sides of bit lines to the first shared node, respectively, and a plurality of second switch circuits for electrically connecting the other end sides to the second shared node, respectively, are provided. In accordance with a column select result, the first and second switch circuit for the corresponding bit line are turned on. Therefore, it is possible to execute a data write operation without providing a driver for each bit line.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: September 9, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takaharu Tsuji, Tsukasa Ooishi
  • Synchronous semiconductor memory device allowing control of operation mode in accordance with operation conditions of a system
    Patent number: 6618319
    Abstract: For a write operation, a synchronous semiconductor memory device in a single-data-rate SDRAM operation mode selects a memory cell column in accordance with a column select signal produced from a write clock produced in synchronization with an external clock signal without shifting the write clock. In a double-data-rate SDRAM operation mode, the synchronous semiconductor memory device selects the memory cell column in accordance with the column select signal produced from the write clock produced in synchronization with the external clock signal and shifted by selected clocks.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: September 9, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tsukasa Ooishi, Masatoshi Ishikawa, Shigeki Tomishima
  • Thin film magnetic memory device having communication function, and distribution management system and manufacturing step management system each using thereof
    Publication number: 20030156449
    Abstract: A thin film magnetic memory device includes an antenna section transmitting and receiving a radio wave to an from an outside of the thin film magnetic memory device. An inductance wiring constituting the antenna section has a metal wiring, and a magnetic film formed to correspond to a lower surface portion of the metal wiring or lower surface and side surface portions of the metal wiring. The magnetic film is formed in an original manufacturing step of the thin film magnetic memory device without providing a dedicated manufacturing step.
    Type: Application
    Filed: August 16, 2002
    Publication date: August 21, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tsukasa Ooishi
  • Non-volatile semiconductor memory device and manufacturing method therefor
    Publication number: 20030157758
    Abstract: A non-volatile semiconductor memory device of the present invention is provided with a semiconductor substrate having a main surface, an ONO film (a laminated film of an oxide film, a nitride film and an oxide film) formed on the main surface and having a charge storage part, a pair of buried diffusion bit lines formed in the semiconductor substrate located on both sides of the ONO film, oxide films deposited on the main surface so as to cover the buried diffusion bit lines, and a transfer gate electrode formed on the ONO film.
    Type: Application
    Filed: August 21, 2002
    Publication date: August 21, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Jun Ohtani, Tsukasa Ooishi
  • Memory device trapping charges in insulating film to store information in non-volatile manner
    Publication number: 20030156457
    Abstract: Dummy cells in an erased state and in a write state are used to generate a dummy current corresponding to the average current of currents flowing in the dummy cells using a ½ current generating circuit, and the dummy current is compared with a current corresponding to a memory cell current flowing in a selected normal cell using a current sense amplification circuit to generate internal read data according to a result of the comparison. With such a configuration, a non-volatile semiconductor memory device capable of reading data at high speed can be achieved.
    Type: Application
    Filed: December 16, 2002
    Publication date: August 21, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tsukasa Ooishi
  • Low-power semiconductor memory device
    Patent number: 6608772
    Abstract: Sense amplifiers are alternately disposed on both sides of bit line pairs, switch circuits are provided so as to selectively connect two bit lines to a sense amplifier, and connection between a sense amplifier and a bit line is switched in accordance with an operation mode. Memory cells are disposed in rows and columns to satisfy the condition that the memory cells are arranged every other row in the same column. A low-power semiconductor memory device with improved access efficiency is provided due to selective activation of the sense amplifiers for reducing the number of the sense amplifiers activated at a time.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: August 19, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tsukasa Ooishi
  • Nonvolatile semiconductor memory device having control circuit
    Publication number: 20030151946
    Abstract: If forward write is performed to a nonvolatile memory cell, a switch signal output circuit outputs a switch signal to a plurality of switch circuits. As a result, corresponding potentials are supplied to a plurality of bit lines, respectively. A potential supply circuit supplies a write potential and a ground potential to the corresponding bit lines, respectively. Therefore, this nonvolatile semiconductor memory device can suppress an unnecessary current generated during data write.
    Type: Application
    Filed: August 13, 2002
    Publication date: August 14, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tsukasa Ooishi
  • Semiconductor memory device having function of supplying stable power supply voltage
    Patent number: 6606274
    Abstract: The inventive semiconductor memory device comprises a synchronous circuit formed by a PLL circuit requiring precise operations, an internal circuit group and a VDC circuit. The VDC circuit, a capacitor, a PMOS transistor for a dummy current and an NMOS transistor serving as a high impedance element are arranged for the synchronous circuit. The VDC circuit is arranged for the internal circuit group. The VDC circuit eliminates power supply noise. The PMOS transistor stabilizes the operation of a differential amplifier of the VDC circuit. The capacitor keeps potential difference between a power supply side and a GND side constant. The NMOS transistor stabilizes the voltage on the GND side.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: August 12, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tsukasa Ooishi, Jun Setogawa
  • Synchronous semiconductor memory device allowing control of operation mode in accordance with operation conditions of a system
    Publication number: 20030147298
    Abstract: For a write operation, a synchronous semiconductor memory device in a single-data-rate SDRAM operation mode selects a memory cell column in accordance with a column select signal produced from a write clock produced in synchronization with an external clock signal without shifting the write clock. In a double-data-rate SDRAM operation mode, the synchronous semiconductor memory device selects the memory cell column in accordance with the column select signal produced from the write clock produced in synchronization with the external clock signal and shifted by selected clocks.
    Type: Application
    Filed: August 2, 2002
    Publication date: August 7, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tsukasa Ooishi, Masatoshi Ishikawa, Shigeki Tomishima
  • Semiconductor circuit device having hierarchical power supply structure
    Patent number: 6603217
    Abstract: Resistance elements are inserted into a main power supply line and a main ground line so that offset differential amplifiers receive voltages developed across the same. The differential amplifiers control transistors connected to a sub power supply line and a sub ground line. Thus, a leakage current flowing from the sub power supply line to the main ground line and that flowing from the main power supply line to the sub ground line are regularly kept constant. Consequently, it is possible to prevent an operation delay in an initial stage of a standby state while keeping an effect of reducing a subthreshold leakage current in a semiconductor circuit device having a hierarchical power supply structure.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: August 5, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tsukasa Ooishi, Hideto Hidaka
  • Semiconductor integrated circuit device capable of ensuring reliability of transistor driving high voltage
    Patent number: 6603685
    Abstract: A driving circuit includes a voltage converting circuit receiving a block selection signal and converting to a signal of a boosted potential level, and first and second N channel MOS transistors connected in series between the boosted potential and the ground potential. The gate of the first transistor receives the boosted potential, and a potential level at a connection node between the first and second transistors is provided as a signal BLI (i, 0).
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: August 5, 2003
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Company Limited
    Inventors: Hideto Hidaka, Hiroaki Tanizaki, Tsukasa Ooishi